--- /dev/null
+From 159153dedc04cc60b9d5cb7970a5afa8cba23fe8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 27 Aug 2022 02:49:39 -0400
+Subject: alpha: fix R_ALPHA_LITERAL reloc for large modules
+
+From: Edward Humes <aurxenon@lunos.org>
+
+[ Upstream commit b6b17a8b3ecd878d98d5472a9023ede9e669ca72 ]
+
+Previously, R_ALPHA_LITERAL relocations would overflow for large kernel
+modules.
+
+This was because the Alpha's apply_relocate_add was relying on the kernel's
+module loader to have sorted the GOT towards the very end of the module as it
+was mapped into memory in order to correctly assign the global pointer. While
+this behavior would mostly work fine for small kernel modules, this approach
+would overflow on kernel modules with large GOT's since the global pointer
+would be very far away from the GOT, and thus, certain entries would be out of
+range.
+
+This patch fixes this by instead using the Tru64 behavior of assigning the
+global pointer to be 32KB away from the start of the GOT. The change made
+in this patch won't work for multi-GOT kernel modules as it makes the
+assumption the module only has one GOT located at the beginning of .got,
+although for the vast majority kernel modules, this should be fine. Of the
+kernel modules that would previously result in a relocation error, none of
+them, even modules like nouveau, have even come close to filling up a single
+GOT, and they've all worked fine under this patch.
+
+Signed-off-by: Edward Humes <aurxenon@lunos.org>
+Signed-off-by: Matt Turner <mattst88@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/alpha/kernel/module.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/arch/alpha/kernel/module.c b/arch/alpha/kernel/module.c
+index 47632fa8c24e0..b169dc9a9ac17 100644
+--- a/arch/alpha/kernel/module.c
++++ b/arch/alpha/kernel/module.c
+@@ -158,10 +158,8 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
+ base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr;
+ symtab = (Elf64_Sym *)sechdrs[symindex].sh_addr;
+
+- /* The small sections were sorted to the end of the segment.
+- The following should definitely cover them. */
+- gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000;
+ got = sechdrs[me->arch.gotsecindex].sh_addr;
++ gp = got + 0x8000;
+
+ for (i = 0; i < n; i++) {
+ unsigned long r_sym = ELF64_R_SYM (rela[i].r_info);
+--
+2.39.2
+
--- /dev/null
+From 53cb843fb86158bb034c539fb5dea73568a58f51 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 11 Jan 2023 08:04:00 +0200
+Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
+
+SPDM is used for debug/profiling and does not have any other
+functionality. These clocks can safely be removed.
+
+Suggested-by: Stephen Boyd <sboyd@kernel.org>
+Suggested-by: Georgi Djakov <djakov@kernel.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
+ 1 file changed, 271 deletions(-)
+
+diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
+index 30777f9f1a439..9c50b5a90e0b6 100644
+--- a/drivers/clk/qcom/mmcc-apq8084.c
++++ b/drivers/clk/qcom/mmcc-apq8084.c
+@@ -2373,262 +2373,6 @@ static struct clk_branch mmss_rbcpr_clk = {
+ },
+ };
+
+-static struct clk_branch mmss_spdm_ahb_clk = {
+- .halt_reg = 0x0230,
+- .clkr = {
+- .enable_reg = 0x0230,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_ahb_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_ahb_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_axi_clk = {
+- .halt_reg = 0x0210,
+- .clkr = {
+- .enable_reg = 0x0210,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_axi_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_axi_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_csi0_clk = {
+- .halt_reg = 0x023c,
+- .clkr = {
+- .enable_reg = 0x023c,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_csi0_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_csi0_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_gfx3d_clk = {
+- .halt_reg = 0x022c,
+- .clkr = {
+- .enable_reg = 0x022c,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_gfx3d_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_gfx3d_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_jpeg0_clk = {
+- .halt_reg = 0x0204,
+- .clkr = {
+- .enable_reg = 0x0204,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_jpeg0_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_jpeg0_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_jpeg1_clk = {
+- .halt_reg = 0x0208,
+- .clkr = {
+- .enable_reg = 0x0208,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_jpeg1_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_jpeg1_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_jpeg2_clk = {
+- .halt_reg = 0x0224,
+- .clkr = {
+- .enable_reg = 0x0224,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_jpeg2_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_jpeg2_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_mdp_clk = {
+- .halt_reg = 0x020c,
+- .clkr = {
+- .enable_reg = 0x020c,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_mdp_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_mdp_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_pclk0_clk = {
+- .halt_reg = 0x0234,
+- .clkr = {
+- .enable_reg = 0x0234,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_pclk0_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_pclk0_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_pclk1_clk = {
+- .halt_reg = 0x0228,
+- .clkr = {
+- .enable_reg = 0x0228,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_pclk1_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_pclk1_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_vcodec0_clk = {
+- .halt_reg = 0x0214,
+- .clkr = {
+- .enable_reg = 0x0214,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_vcodec0_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_vcodec0_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_vfe0_clk = {
+- .halt_reg = 0x0218,
+- .clkr = {
+- .enable_reg = 0x0218,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_vfe0_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_vfe0_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_vfe1_clk = {
+- .halt_reg = 0x021c,
+- .clkr = {
+- .enable_reg = 0x021c,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_vfe1_clk",
+- .parent_names = (const char *[]){
+- "mmss_spdm_vfe1_div_clk",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_rm_axi_clk = {
+- .halt_reg = 0x0304,
+- .clkr = {
+- .enable_reg = 0x0304,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_rm_axi_clk",
+- .parent_names = (const char *[]){
+- "mmss_axi_clk_src",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
+- .halt_reg = 0x0308,
+- .clkr = {
+- .enable_reg = 0x0308,
+- .enable_mask = BIT(0),
+- .hw.init = &(struct clk_init_data){
+- .name = "mmss_spdm_rm_ocmemnoc_clk",
+- .parent_names = (const char *[]){
+- "ocmemnoc_clk_src",
+- },
+- .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
+- .ops = &clk_branch2_ops,
+- },
+- },
+-};
+-
+-
+ static struct clk_branch mmss_misc_ahb_clk = {
+ .halt_reg = 0x502c,
+ .clkr = {
+@@ -3261,21 +3005,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
+ [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
+ [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
+ [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
+- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
+- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
+- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
+- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
+- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
+- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
+- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
+- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
+- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
+- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
+- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
+- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
+- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
+- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
+- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
+ [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
+ [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
+ [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
+--
+2.39.2
+
--- /dev/null
+From 5787b0ce29dfe622875d9c2d4878e571087ed4b9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 15 Feb 2023 10:12:12 -0700
+Subject: macintosh: windfarm: Use unsigned type for 1-bit bitfields
+
+From: Nathan Chancellor <nathan@kernel.org>
+
+[ Upstream commit 748ea32d2dbd813d3bd958117bde5191182f909a ]
+
+Clang warns:
+
+ drivers/macintosh/windfarm_lm75_sensor.c:63:14: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
+ lm->inited = 1;
+ ^ ~
+
+ drivers/macintosh/windfarm_smu_sensors.c:356:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
+ pow->fake_volts = 1;
+ ^ ~
+ drivers/macintosh/windfarm_smu_sensors.c:368:18: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
+ pow->quadratic = 1;
+ ^ ~
+
+There is no bug here since no code checks the actual value of these
+fields, just whether or not they are zero (boolean context), but this
+can be easily fixed by switching to an unsigned type.
+
+Signed-off-by: Nathan Chancellor <nathan@kernel.org>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20230215-windfarm-wsingle-bit-bitfield-constant-conversion-v1-1-26415072e855@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/macintosh/windfarm_lm75_sensor.c | 4 ++--
+ drivers/macintosh/windfarm_smu_sensors.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/macintosh/windfarm_lm75_sensor.c b/drivers/macintosh/windfarm_lm75_sensor.c
+index 6cdfe714901d5..1332fc789056a 100644
+--- a/drivers/macintosh/windfarm_lm75_sensor.c
++++ b/drivers/macintosh/windfarm_lm75_sensor.c
+@@ -34,8 +34,8 @@
+ #endif
+
+ struct wf_lm75_sensor {
+- int ds1775 : 1;
+- int inited : 1;
++ unsigned int ds1775 : 1;
++ unsigned int inited : 1;
+ struct i2c_client *i2c;
+ struct wf_sensor sens;
+ };
+diff --git a/drivers/macintosh/windfarm_smu_sensors.c b/drivers/macintosh/windfarm_smu_sensors.c
+index 172fd267dcf60..0f4017a8189e5 100644
+--- a/drivers/macintosh/windfarm_smu_sensors.c
++++ b/drivers/macintosh/windfarm_smu_sensors.c
+@@ -275,8 +275,8 @@ struct smu_cpu_power_sensor {
+ struct list_head link;
+ struct wf_sensor *volts;
+ struct wf_sensor *amps;
+- int fake_volts : 1;
+- int quadratic : 1;
++ unsigned int fake_volts : 1;
++ unsigned int quadratic : 1;
+ struct wf_sensor sens;
+ };
+ #define to_smu_cpu_power(c) container_of(c, struct smu_cpu_power_sensor, sens)
+--
+2.39.2
+
--- /dev/null
+From e6d06d70125906d5dc3c7923da64b79f4abdc15d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 28 Nov 2022 09:02:01 +0100
+Subject: media: ov5640: Fix analogue gain control
+
+From: Paul Elder <paul.elder@ideasonboard.com>
+
+[ Upstream commit afa4805799c1d332980ad23339fdb07b5e0cf7e0 ]
+
+Gain control is badly documented in publicly available (including
+leaked) documentation.
+
+There is an AGC pre-gain in register 0x3a13, expressed as a 6-bit value
+(plus an enable bit in bit 6). The driver hardcodes it to 0x43, which
+one application note states is equal to x1.047. The documentation also
+states that 0x40 is equel to x1.000. The pre-gain thus seems to be
+expressed as in 1/64 increments, and thus ranges from x1.00 to x1.984.
+What the pre-gain does is however unspecified.
+
+There is then an AGC gain limit, in registers 0x3a18 and 0x3a19,
+expressed as a 10-bit "real gain format" value. One application note
+sets it to 0x00f8 and states it is equal to x15.5, so it appears to be
+expressed in 1/16 increments, up to x63.9375.
+
+The manual gain is stored in registers 0x350a and 0x350b, also as a
+10-bit "real gain format" value. It is documented in the application
+note as a Q6.4 values, up to x63.9375.
+
+One version of the datasheet indicates that the sensor supports a
+digital gain:
+
+ The OV5640 supports 1/2/4 digital gain. Normally, the gain is
+ controlled automatically by the automatic gain control (AGC) block.
+
+It isn't clear how that would be controlled manually.
+
+There appears to be no indication regarding whether the gain controlled
+through registers 0x350a and 0x350b is an analogue gain only or also
+includes digital gain. The words "real gain" don't necessarily mean
+"combined analogue and digital gains". Some OmniVision sensors (such as
+the OV8858) are documented as supoprting different formats for the gain
+values, selectable through a register bit, and they are called "real
+gain format" and "sensor gain format". For that sensor, we have (one of)
+the gain registers documented as
+
+ 0x3503[2]=0, gain[7:0] is real gain format, where low 4 bits are
+ fraction bits, for example, 0x10 is 1x gain, 0x28 is 2.5x gain
+
+ If 0x3503[2]=1, gain[7:0] is sensor gain format, gain[7:4] is coarse
+ gain, 00000: 1x, 00001: 2x, 00011: 4x, 00111: 8x, gain[7] is 1,
+ gain[3:0] is fine gain. For example, 0x10 is 1x gain, 0x30 is 2x gain,
+ 0x70 is 4x gain
+
+(The second part of the text makes little sense)
+
+"Real gain" may thus refer to the combination of the coarse and fine
+analogue gains as a single value.
+
+The OV5640 0x350a and 0x350b registers thus appear to control analogue
+gain. The driver incorrectly uses V4L2_CID_GAIN as V4L2 has a specific
+control for analogue gain, V4L2_CID_ANALOGUE_GAIN. Use it.
+
+If registers 0x350a and 0x350b are later found to control digital gain
+as well, the driver could then restrict the range of the analogue gain
+control value to lower than x64 and add a separate digital gain control.
+
+Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
+Reviewed-by: Jai Luthra <j-luthra@ti.com>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/ov5640.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index eb0331b8a5833..b78e35425d14f 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2002,7 +2002,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ /* Auto/manual gain */
+ ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
+ 0, 1, 1, 1);
+- ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
++ ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
+ 0, 1023, 1, 0);
+
+ ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
+--
+2.39.2
+
--- /dev/null
+From bb3d2e14fd177de0fa78c1c72f1d1fe4753b7f87 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 18 Jan 2023 16:59:12 +0800
+Subject: MIPS: Fix a compilation issue
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: xurui <xurui@kylinos.cn>
+
+[ Upstream commit 109d587a4b4d7ccca2200ab1f808f43ae23e2585 ]
+
+arch/mips/include/asm/mach-rc32434/pci.h:377:
+cc1: error: result of β-117440512 << 16β requires 44 bits to represent, but βintβ only has 32 bits [-Werror=shift-overflow=]
+
+All bits in KORINA_STAT are already at the correct position, so there is
+no addtional shift needed.
+
+Signed-off-by: xurui <xurui@kylinos.cn>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/include/asm/mach-rc32434/pci.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
+index 6f40d1515580b..1ff8a987025c8 100644
+--- a/arch/mips/include/asm/mach-rc32434/pci.h
++++ b/arch/mips/include/asm/mach-rc32434/pci.h
+@@ -377,7 +377,7 @@ struct pci_msu {
+ PCI_CFG04_STAT_SSE | \
+ PCI_CFG04_STAT_PE)
+
+-#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
++#define KORINA_CNFG1 (KORINA_STAT | KORINA_CMD)
+
+ #define KORINA_REVID 0
+ #define KORINA_CLASS_CODE 0
+--
+2.39.2
+
--- /dev/null
+From 41421e7c5edd580028601bf791cd562d35be47bc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 Jan 2023 18:56:36 +0200
+Subject: PCI: Add SolidRun vendor ID
+
+From: Alvaro Karsz <alvaro.karsz@solid-run.com>
+
+[ Upstream commit db6c4dee4c104f50ed163af71c53bfdb878a8318 ]
+
+Add SolidRun vendor ID to pci_ids.h
+
+The vendor ID is used in 2 different source files, the SNET vDPA driver
+and PCI quirks.
+
+Signed-off-by: Alvaro Karsz <alvaro.karsz@solid-run.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Message-Id: <20230110165638.123745-2-alvaro.karsz@solid-run.com>
+Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index d4eae72202fab..0122286beda53 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -3045,6 +3045,8 @@
+
+ #define PCI_VENDOR_ID_3COM_2 0xa727
+
++#define PCI_VENDOR_ID_SOLIDRUN 0xd063
++
+ #define PCI_VENDOR_ID_DIGIUM 0xd161
+ #define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410
+
+--
+2.39.2
+
--- /dev/null
+From d352002f6b67a6d88586d896cd13d5e8b5c7956a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 Jan 2023 18:56:37 +0200
+Subject: PCI: Avoid FLR for SolidRun SNET DPU rev 1
+
+From: Alvaro Karsz <alvaro.karsz@solid-run.com>
+
+[ Upstream commit d089d69cc1f824936eeaa4fa172f8fa1a0949eaa ]
+
+This patch fixes a FLR bug on the SNET DPU rev 1 by setting the
+PCI_DEV_FLAGS_NO_FLR_RESET flag.
+
+As there is a quirk to avoid FLR (quirk_no_flr), I added a new quirk
+to check the rev ID before calling to quirk_no_flr.
+
+Without this patch, a SNET DPU rev 1 may hang when FLR is applied.
+
+Signed-off-by: Alvaro Karsz <alvaro.karsz@solid-run.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Message-Id: <20230110165638.123745-3-alvaro.karsz@solid-run.com>
+Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index b9fedf9c77cb9..d0bff9a9f9a9c 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5068,6 +5068,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
+
++/* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
++static void quirk_no_flr_snet(struct pci_dev *dev)
++{
++ if (dev->revision == 0x1)
++ quirk_no_flr(dev);
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
++
+ static void quirk_no_ext_tags(struct pci_dev *pdev)
+ {
+ struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
+--
+2.39.2
+
nfc-fdp-add-null-check-of-devm_kmalloc_array-in-fdp_.patch
ila-do-not-generate-empty-messages-in-ila_xlat_nl_cm.patch
net-caif-fix-use-after-free-in-cfusbl_device_notify.patch
+clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
+mips-fix-a-compilation-issue.patch
+alpha-fix-r_alpha_literal-reloc-for-large-modules.patch
+macintosh-windfarm-use-unsigned-type-for-1-bit-bitfi.patch
+pci-add-solidrun-vendor-id.patch
+pci-avoid-flr-for-solidrun-snet-dpu-rev-1.patch
+media-ov5640-fix-analogue-gain-control.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
