]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: correct PHY register offset for PHY-1
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 9 Feb 2024 06:52:19 +0000 (14:52 +0800)
committerKalle Valo <kvalo@kernel.org>
Mon, 12 Feb 2024 15:39:12 +0000 (17:39 +0200)
PHY-1 can be seen as a copy of PHY-0, and the difference is their base
register address, so add a function to get offset to access PHY-1.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20240209065229.34515-2-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/phy.c
drivers/net/wireless/realtek/rtw89/phy.h
drivers/net/wireless/realtek/rtw89/phy_be.c

index 9a8f5b764617e119fcc16fc07644116ac6a4d056..7c2f0ba996b1e7f1e3aced98785bf1a7b28acebd 100644 (file)
 #include "txrx.h"
 #include "util.h"
 
+static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
+{
+       const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+
+       return phy->phy0_phy1_offset(rtwdev, addr);
+}
+
 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
                             const struct rtw89_ra_report *report)
 {
@@ -1633,14 +1640,11 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
                rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
 }
 
-static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
+static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
 {
        u32 phy_page = addr >> 8;
        u32 ofst = 0;
 
-       if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
-               return addr < 0x10000 ? 0x20000 : 0;
-
        switch (phy_page) {
        case 0x6:
        case 0x7:
@@ -6392,6 +6396,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
        .ccx = &rtw89_ccx_regs_ax,
        .physts = &rtw89_physts_regs_ax,
        .cfo = &rtw89_cfo_regs_ax,
+       .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
        .config_bb_gain = rtw89_phy_config_bb_gain_ax,
        .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
        .bb_wrap_init = NULL,
index d80ddc723e8644d3a10bf6876b61ccc69924ed38..76234daab896d355fedaaaf4aa97b920253a450c 100644 (file)
@@ -510,6 +510,7 @@ struct rtw89_phy_gen_def {
        const struct rtw89_ccx_regs *ccx;
        const struct rtw89_physts_regs *physts;
        const struct rtw89_cfo_regs *cfo;
+       u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
        void (*config_bb_gain)(struct rtw89_dev *rtwdev,
                               const struct rtw89_reg2_def *reg,
                               enum rtw89_rf_path rf_path,
index 6849438a5f3cc7426d59ae3898b7535d092ad845..be0148f2b96f42741a85817866daa64d78ef175e 100644 (file)
@@ -78,6 +78,24 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_be = {
        .valid_0_mask = B_DCFO_OPT_EN_V1,
 };
 
+static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
+{
+       u32 phy_page = addr >> 8;
+       u32 ofst = 0;
+
+       if ((phy_page >= 0x4 && phy_page <= 0xF) ||
+           (phy_page >= 0x20 && phy_page <= 0x2B) ||
+           (phy_page >= 0x40 && phy_page <= 0x4f) ||
+           (phy_page >= 0x60 && phy_page <= 0x6f) ||
+           (phy_page >= 0xE4 && phy_page <= 0xE5) ||
+           (phy_page >= 0xE8 && phy_page <= 0xED))
+               ofst = 0x1000;
+       else
+               ofst = 0x0;
+
+       return ofst;
+}
+
 union rtw89_phy_bb_gain_arg_be {
        u32 addr;
        struct {
@@ -952,6 +970,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
        .ccx = &rtw89_ccx_regs_be,
        .physts = &rtw89_physts_regs_be,
        .cfo = &rtw89_cfo_regs_be,
+       .phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
        .config_bb_gain = rtw89_phy_config_bb_gain_be,
        .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
        .bb_wrap_init = rtw89_phy_bb_wrap_init_be,