zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini-emmc0.dtb \
- versal-mini-emmc1.dtb
+ versal-mini-emmc1.dtb \
+ versal-mini-qspi-parallel.dtb \
+ versal-mini-qspi-single.dtb \
+ versal-mini-qspi-stacked.dtb \
+ versal-mini-qspi-x1-single.dtb \
+ versal-mini-qspi-x1-stacked.dtb \
+ versal-mini-qspi-x2-single.dtb \
+ versal-mini-qspi-x2-stacked.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <1>;
+};
+
+&flash0 {
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&flash0 {
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ is-stacked = <1>;
+};
+
+&flash0 {
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&flash0 {
+ spi-rx-bus-width = <1>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ is-stacked = <1>;
+};
+
+&flash0 {
+ spi-rx-bus-width = <1>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&flash0 {
+ spi-rx-bus-width = <2>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ is-stacked = <1>;
+};
+
+&flash0 {
+ spi-rx-bus-width = <2>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini QSPI Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Xilinx Versal MINI QSPI";
+
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <125000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <0x1>;
+ reg = <0x0 0xf1030000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #stream-id-cells = <1>;
+ clocks = <&clk125 &clk125>;
+
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80", "spi-flash";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0x0 0xfffc0000 0x0 0x40000>;
+ };
+};
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_ARCH_VERSAL=y
+CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x2000
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_COUNTER_FREQUENCY=2720000
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_IMAGE_FORMAT_LEGACY is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+CONFIG_SYS_PROMPT="Versal> "
+# CONFIG_AUTOBOOT is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_GENERIC=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for Xilinx Versal QSPI Flash utility
+ *
+ * (C) Copyright 2018-2019 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_VERSAL_MINI_QSPI_H
+#define __CONFIG_VERSAL_MINI_QSPI_H
+
+#include <configs/xilinx_versal_mini.h>
+
+#undef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
+
+#endif /* __CONFIG_VERSAL_MINI_QSPI_H */