selftests/bpf: Enable arena atomics tests for RV64

Enable arena atomics tests for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20250719091730.2660197-11-pulehui@huaweicloud.com

diff --git a/tools/testing/selftests/bpf/progs/arena_atomics.c b/tools/testing/selftests/bpf/progs/arena_atomics.c
index a52feff98112646c4951c9d5fa7ae8b6fdfc2e50..d1841aac94a22f646fc9a767104e47a6e8353d2b 100644 (file)
--- a/tools/testing/selftests/bpf/progs/arena_atomics.c
+++ b/tools/testing/selftests/bpf/progs/arena_atomics.c
@@ -28,7 +28,8 @@ bool skip_all_tests = true;
 
 #if defined(ENABLE_ATOMICS_TESTS) &&             \
        defined(__BPF_FEATURE_ADDR_SPACE_CAST) && \
-       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86))
+       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+        (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64))
 bool skip_lacq_srel_tests __attribute((__section__(".data"))) = false;
 #else
 bool skip_lacq_srel_tests = true;
@@ -314,7 +315,8 @@ int load_acquire(const void *ctx)
 {
 #if defined(ENABLE_ATOMICS_TESTS) &&             \
        defined(__BPF_FEATURE_ADDR_SPACE_CAST) && \
-       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86))
+       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+        (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64))
 
 #define LOAD_ACQUIRE_ARENA(SIZEOP, SIZE, SRC, DST)     \
        { asm volatile (                                \
@@ -365,7 +367,8 @@ int store_release(const void *ctx)
 {
 #if defined(ENABLE_ATOMICS_TESTS) &&             \
        defined(__BPF_FEATURE_ADDR_SPACE_CAST) && \
-       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86))
+       (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+        (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64))
 
 #define STORE_RELEASE_ARENA(SIZEOP, DST, VAL)  \
        { asm volatile (                        \