--- /dev/null
+From bp@alien8.de Sat Jul 12 14:02:17 2025
+From: Borislav Petkov <bp@alien8.de>
+Date: Fri, 11 Jul 2025 21:23:58 +0200
+Subject: x86/CPU/AMD: Properly check the TSA microcode
+To: stable@vger.kernel.org
+Cc: Thomas Voegtle <tv@lio96.de>, kim.phillips@amd.com
+Message-ID: <20250711192358.GJaHFkzpM1GPcNQz6v@fat_crate.local>
+Content-Disposition: inline
+
+
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+
+In order to simplify backports, I resorted to an older version of the
+microcode revision checking which didn't pull in the whole struct
+x86_cpu_id matching machinery.
+
+My simpler method, however, forgot to add the extended CPU model to the
+patch revision, which lead to mismatches when determining whether TSA
+mitigation support is present.
+
+So add that forgotten extended model.
+
+This is a stable-only fix and the preference is to do it this way
+because it is a lot simpler. Also, the Fixes: tag below points to the
+respective stable patch.
+
+Fixes: 90293047df18 ("x86/bugs: Add a Transient Scheduler Attacks mitigation")
+Reported-by: Thomas Voegtle <tv@lio96.de>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Tested-by: Thomas Voegtle <tv@lio96.de>
+Message-ID: <04ea0a8e-edb0-c59e-ce21-5f3d5d167af3@lio96.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/amd.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -547,6 +547,7 @@ static bool amd_check_tsa_microcode(void
+
+ p.ext_fam = c->x86 - 0xf;
+ p.model = c->x86_model;
++ p.ext_model = c->x86_model >> 4;
+ p.stepping = c->x86_stepping;
+
+ if (cpu_has(c, X86_FEATURE_ZEN3) ||