RDMA/bnxt_re: Fix the GID table length

GID table length is reported by FW. The gid index which is passed to the
driver during modify_qp/create_ah is restricted by the sgid_index field of
struct ib_global_route.  sgid_index is u8 and the max sgid possible is
256.

Each GID entry in HW will have 2 GID entries in the kernel gid table.  So
we can support twice the gid table size reported by FW. Also, restrict the
max GID to 256 also.

Fixes: 847b97887ed4 ("RDMA/bnxt_re: Restrict the max_gids to 256")
Link: https://patch.msgid.link/r/1728373302-19530-11-git-send-email-selvin.xavier@broadcom.com
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
index 32c1cc79bd6802a3f8c4f8781e1180789a4648a1..e29fbbdab9fd683931c8258471f803979ec9212a 100644 (file)
--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
@@ -159,7 +159,14 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
        if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
                attr->l2_db_size = (sb->l2_db_space_size + 1) *
                                    (0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
-       attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;
+       /*
+        * Read the max gid supported by HW.
+        * For each entry in HW  GID in HW table, we consume 2
+        * GID entries in the kernel GID table.  So max_gid reported
+        * to stack can be up to twice the value reported by the HW, up to 256 gids.
+        */
+       attr->max_sgid = le32_to_cpu(sb->max_gid);
+       attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid);
        attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
        attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2);