5.4-stable patches

added patches:
	soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch

diff --git a/queue-5.4/series b/queue-5.4/series
new file mode 100644 (file)
index 0000000..a751836
--- /dev/null
+++ b/queue-5.4/series
@@ -0,0 +1 @@
+soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch

diff --git a/queue-5.4/soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch b/queue-5.4/soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch
new file mode 100644 (file)
index 0000000..ea7b3c2
--- /dev/null
+++ b/queue-5.4/soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch
@@ -0,0 +1,35 @@
+From 19221e3083020bd9537624caa0ee0145ed92ba36 Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <digetx@gmail.com>
+Date: Tue, 2 Mar 2021 15:24:58 +0300
+Subject: soc/tegra: pmc: Fix imbalanced clock disabling in error code path
+
+From: Dmitry Osipenko <digetx@gmail.com>
+
+commit 19221e3083020bd9537624caa0ee0145ed92ba36 upstream.
+
+The tegra_powergate_power_up() has a typo in the error code path where it
+will try to disable clocks twice, fix it. In practice that error never
+happens, so this is a minor correction.
+
+Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
+Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
+Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/soc/tegra/pmc.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/soc/tegra/pmc.c
++++ b/drivers/soc/tegra/pmc.c
+@@ -579,7 +579,7 @@ static int tegra_powergate_power_up(stru
+ 
+       err = tegra_powergate_enable_clocks(pg);
+       if (err)
+-              goto disable_clks;
++              goto powergate_off;
+ 
+       usleep_range(10, 20);
+