RISC-V: Enforce Libatomic LR/SC SEQ_CST

Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

libgcc/ChangeLog:

	* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
	sequentially consistent LR.aqrl/SC.rl pairs.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c
index 573d163ea049eef7fc9db06a909281a2d1af71cc..bd2b033132baf7f50220187d73afdf4c65cd3b00 100644 (file)
--- a/libgcc/config/riscv/atomic.c
+++ b/libgcc/config/riscv/atomic.c
@@ -41,7 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     unsigned old, tmp1, tmp2;                                          \
                                                                        \
     asm volatile ("1:\n\t"                                             \
-                 "lr.w.aq %[old], %[mem]\n\t"                          \
+                 "lr.w.aqrl %[old], %[mem]\n\t"                        \
                  #insn " %[tmp1], %[old], %[value]\n\t"                \
                  invert                                                \
                  "and %[tmp1], %[tmp1], %[mask]\n\t"                   \
@@ -75,7 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     unsigned old, tmp1;                                                        \
                                                                        \
     asm volatile ("1:\n\t"                                             \
-                 "lr.w.aq %[old], %[mem]\n\t"                          \
+                 "lr.w.aqrl %[old], %[mem]\n\t"                        \
                  "and %[tmp1], %[old], %[mask]\n\t"                    \
                  "bne %[tmp1], %[o], 1f\n\t"                           \
                  "and %[tmp1], %[old], %[not_mask]\n\t"                \