mips.md (move_doubleword_fpr<mode>): Use TARGET_FLOAT64 && !TARGET_64BIT to detect...

gcc/
	* config/mips/mips.md (move_doubleword_fpr<mode>): Use
	TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case.

From-SVN: r142769

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a5314980c244cc467a50e092d51f101b8ab98480..aeed7051e485f7adf8460dbd98c953f097dde3e7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2008-12-15  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/mips/mips.md (move_doubleword_fpr<mode>): Use
+       TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case.
+
 2008-12-15  Hariharan Sandanagobalane <hariharan@picochip.com>
 
        * config/picochip/picochip.c (picochip_override_options): Disable CFI

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 1b26f0298539af529446e279519a281348c2d6b4..5a06cdc7e714c89025a49c98caf7a9726aa3af9a 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4521,8 +4521,8 @@
       rtx low = mips_subword (operands[1], 0);
       rtx high = mips_subword (operands[1], 1);
       emit_insn (gen_load_low<mode> (operands[0], low));
-      if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode))
-       emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
+      if (TARGET_FLOAT64 && !TARGET_64BIT)
+       emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
       else
        emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
     }
@@ -4531,7 +4531,7 @@
       rtx low = mips_subword (operands[0], 0);
       rtx high = mips_subword (operands[0], 1);
       emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
-      if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode))
+      if (TARGET_FLOAT64 && !TARGET_64BIT)
        emit_insn (gen_mfhc1<mode> (high, operands[1]));
       else
        emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));