expressionS ex;
elf_suffix_type suffix;
bfd_reloc_code_real_type reloc;
- int skip_optional;
+ int omitted_base_or_index;
char *f;
int fc, i;
while (ISSPACE (*str))
str++;
- skip_optional = 0;
-
/* Gather the operands. */
+ omitted_base_or_index = 0; /* Whether B in D(L,B) or X in D(X,B) were omitted. */
fc = 0;
for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
{
break;
}
- if (skip_optional && (operand->flags & S390_OPERAND_INDEX))
+ if (omitted_base_or_index && (operand->flags & S390_OPERAND_INDEX))
{
- /* We do an early skip. For D(X,B) constructions the index
- register is skipped (X is optional). For D(L,B) the base
- register will be the skipped operand, because L is NOT
- optional. */
- skip_optional = 0;
+ /* Skip omitted optional index register operand in D(X,B) due to
+ D(,B) or D(B). Skip comma, if D(,B). */
+ if (*str == ',')
+ str++;
+ omitted_base_or_index = 0;
continue;
}
for (f = str; *f != '\0'; f++)
if (*f == ',' || *f == ')')
break;
- /* If there is no comma until the closing parentheses OR
- there is a comma right after the opening parentheses,
- we have to skip optional operands. */
+ /* If there is no comma until the closing parenthesis ')' or
+ there is a comma right after the opening parenthesis '(',
+ we have to skip the omitted optional index or base register
+ operand:
+ - Index X in D(X,B), when D(,B) or D(B)
+ - Base B in D(L,B), when D(L) */
if (*f == ',' && f == str)
{
- /* comma directly after '(' ? */
- skip_optional = 1;
- str++;
+ /* Comma directly after opening parenthesis '(' ? */
+ omitted_base_or_index = 1;
}
else
- skip_optional = (*f != ',');
+ omitted_base_or_index = (*f != ',');
}
}
else if (operand->flags & S390_OPERAND_BASE)
as_bad (_("syntax error; missing ')' after base register"));
else
str++;
- skip_optional = 0;
+ omitted_base_or_index = 0;
if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1]))
continue;
run_list_test "machine-parsing-4" ""
run_list_test "machine-parsing-5" ""
run_list_test "machine-parsing-6" ""
+ run_dump_test "zarch-omitted-base-index" "{as -m64}"
+ run_list_test "zarch-omitted-base-index-err" ""
}
--- /dev/null
+.*: Assembler messages:
+.*:5: Error: bad expression
+.*:5: Error: syntax error; missing '\)' after base register
+.*:8: Error: bad expression
+.*:8: Error: syntax error; missing '\)' after base register
+.*:9: Error: bad expression
+.*:9: Error: syntax error; missing '\)' after base register
+.*:12: Error: bad expression
+.*:12: Error: syntax error; missing '\)' after base register
+.*:13: Error: bad expression
+.*:13: Error: syntax error; missing '\)' after base register
+.*:16: Error: missing operand
+.*:17: Error: missing operand
+.*:18: Error: invalid length field specified
+.*:19: Error: bad expression
+.*:19: Error: operand out of range \(0 is not between 1 and 256\)
+.*:19: Error: operand out of range \(32 is not between 0 and 15\)
+.*:19: Error: syntax error; missing '\)' after base register
+.*:19: Error: syntax error; expected ','
+.*:19: Error: bad expression
+.*:19: Error: found 'r', expected: '\)'
+.*:19: Error: syntax error; missing '\)' after base register
+.*:19: Error: junk at end of line: `r2\)'
+.*:20: Error: syntax error; missing '\(' after displacement
--- /dev/null
+.text
+foo:
+
+# R1,D2(B2)
+ clm %r1,0b1000,16()
+
+# R1,D2(X2,B2)
+ a %r1,16(%r2,)
+ a %r1,16()
+
+# V1,D2(VX2,B2),M3
+ vgef %v1,16(%v2,),0
+ vgef %v1,16(),0
+
+# D1(L1,B1),D2(B2)
+ mvc 16(,%r1),32(%r2)
+ mvc 16(,1),32(%r2)
+ mvc 16(%r1),32(%r2)
+ mvc 16(),32(%r2)
+ mvc 16,32(%r2)
--- /dev/null
+#name: s390x omit base/index register
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*: bd 18 20 10 [ ]*clm %r1,8,16\(%r2\)
+.*: bd 18 00 10 [ ]*clm %r1,8,16
+.*: 5a 12 30 10 [ ]*a %r1,16\(%r2,%r3\)
+.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\)
+.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\)
+.*: 5a 10 00 10 [ ]*a %r1,16
+.*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0
+.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
+.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
+.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0
+.*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\)
+.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32
+.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\)
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
--- /dev/null
+.text
+foo:
+
+# R1,D2(B2)
+ clm %r1,0b1000,16(%r2)
+ clm %r1,0b1000,16
+
+# R1,D1(X2,B2)
+ a %r1,16(%r2,%r3)
+ a %r1,16(,%r3)
+ a %r1,16(%r3)
+ a %r1,16
+
+# V1,D2(VX2,B2),M3
+ vgef %v1,16(%v2,%r3),0
+ vgef %v1,16(,%r3),0
+ vgef %v1,16(%r3),0
+ vgef %v1,16,0
+
+# D1(L1,B1),D2(B2)
+ mvc 16(1,%r1),32(%r2)
+ mvc 16(1,%r1),32
+ mvc 16(1),32(%r2)
+ mvc 16(1),32