drm/amd/pm: Show default gfx clock levels

For SMU v13.0.6 SOCs, always show default clock levels for gfx in
pp_dpm_sclk. Any custom min/max levels set by user will be available in
pp_od_clk_voltage

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index f00ef7f3f3551a58e3e76aeb0ed004707c456659..f419472fd749279a08b428e0905e28e5a7bb0e2b 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -1377,8 +1377,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
                        return ret;
                }
 
-               min_clk = pstate_table->gfxclk_pstate.curr.min;
-               max_clk = pstate_table->gfxclk_pstate.curr.max;
+               single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
+               min_clk = single_dpm_table->min;
+               max_clk = single_dpm_table->max;
 
                if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
                        size += sysfs_emit_at(buf, size, "S: %uMhz *\n",