drm/i915/wm: convert i9xx_wm.h external interfaces to struct intel_display

Going forward, struct intel_display is the main display device data
pointer. Convert the i9xx_wm.h interface to struct intel_display.

With this, we can make intel_wm.c independent of i915_drv.h.

v2: Also remove i915_drv.h, fix commit message

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/3e30634d85c0e0aac9c95f9a2f928131ba400271.1744119460.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index e6a1b9b10b0183d6b61dbbb38ca34ae5e5fd0969..7202ef503e58d226e65fa44a081c93569e71a20d 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -200,7 +200,7 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
 
 /**
  * intel_set_memory_cxsr - Configure CxSR state
- * @dev_priv: i915 device
+ * @display: display device
  * @enable: Allow vs. disallow CxSR
  *
  * Allow or disallow the system to enter a special CxSR
@@ -235,8 +235,9 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
  * the hardware w.r.t. HPLL SR when writing to plane registers.
  * Disallowing just CxSR is sufficient.
  */
-bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
+bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
 {
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
        bool ret;
 
        mutex_lock(&dev_priv->display.wm.wm_mutex);
@@ -652,7 +653,7 @@ static void pnv_update_wm(struct intel_display *display)
        latency = pnv_get_cxsr_latency(dev_priv);
        if (!latency) {
                drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
-               intel_set_memory_cxsr(dev_priv, false);
+               intel_set_memory_cxsr(display, false);
                return;
        }
 
@@ -702,9 +703,9 @@ static void pnv_update_wm(struct intel_display *display)
                intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
                drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 
-               intel_set_memory_cxsr(dev_priv, true);
+               intel_set_memory_cxsr(display, true);
        } else {
-               intel_set_memory_cxsr(dev_priv, false);
+               intel_set_memory_cxsr(display, false);
        }
 }
 
@@ -2177,7 +2178,7 @@ static void i965_update_wm(struct intel_display *display)
        } else {
                cxsr_enabled = false;
                /* Turn off self refresh if both pipes are enabled */
-               intel_set_memory_cxsr(dev_priv, false);
+               intel_set_memory_cxsr(display, false);
        }
 
        drm_dbg_kms(&dev_priv->drm,
@@ -2198,7 +2199,7 @@ static void i965_update_wm(struct intel_display *display)
                           FW_WM(cursor_sr, CURSOR_SR));
 
        if (cxsr_enabled)
-               intel_set_memory_cxsr(dev_priv, true);
+               intel_set_memory_cxsr(display, true);
 }
 
 #undef FW_WM
@@ -2307,7 +2308,7 @@ static void i9xx_update_wm(struct intel_display *display)
        cwm = 2;
 
        /* Play safe and disable self-refresh before adjusting watermarks. */
-       intel_set_memory_cxsr(dev_priv, false);
+       intel_set_memory_cxsr(display, false);
 
        /* Calc sr entries for one plane configs */
        if (HAS_FW_BLC(dev_priv) && crtc) {
@@ -2359,7 +2360,7 @@ static void i9xx_update_wm(struct intel_display *display)
        intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
 
        if (crtc)
-               intel_set_memory_cxsr(dev_priv, true);
+               intel_set_memory_cxsr(display, true);
 }
 
 static void i845_update_wm(struct intel_display *display)
@@ -3411,8 +3412,10 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
        dev_priv->display.wm.hw = *results;
 }
 
-bool ilk_disable_cxsr(struct drm_i915_private *dev_priv)
+bool ilk_disable_cxsr(struct intel_display *display)
 {
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
+
        return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
@@ -3580,8 +3583,9 @@ static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
  * through the atomic check code to calculate new watermark values in the
  * state object.
  */
-void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
+void ilk_wm_sanitize(struct intel_display *display)
 {
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
        struct drm_atomic_state *state;
        struct intel_atomic_state *intel_state;
        struct intel_crtc *crtc;
@@ -4156,8 +4160,10 @@ static const struct intel_wm_funcs i845_wm_funcs = {
 static const struct intel_wm_funcs nop_funcs = {
 };
 
-void i9xx_wm_init(struct drm_i915_private *dev_priv)
+void i9xx_wm_init(struct intel_display *display)
 {
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
+
        /* For FIFO watermark updates */
        if (HAS_PCH_SPLIT(dev_priv)) {
                ilk_setup_wm_latency(dev_priv);
@@ -4172,7 +4178,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
                if (!pnv_get_cxsr_latency(dev_priv)) {
                        drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
                        /* Disable CxSR and never update its watermark again */
-                       intel_set_memory_cxsr(dev_priv, false);
+                       intel_set_memory_cxsr(display, false);
                        dev_priv->display.funcs.wm = &nop_funcs;
                } else {
                        dev_priv->display.funcs.wm = &pnv_wm_funcs;

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h
index 06ac37c6c94b5b986be36cfb8d6f8f1ee5c4ce9b..7bb363b2a756388528fa1e8844acfc96d8afd4ab 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.h
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.h
@@ -8,28 +8,28 @@
 
 #include <linux/types.h>
 
-struct drm_i915_private;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_plane_state;
 
 #ifdef I915
-bool ilk_disable_cxsr(struct drm_i915_private *i915);
-void ilk_wm_sanitize(struct drm_i915_private *i915);
-bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
-void i9xx_wm_init(struct drm_i915_private *i915);
+bool ilk_disable_cxsr(struct intel_display *display);
+void ilk_wm_sanitize(struct intel_display *display);
+bool intel_set_memory_cxsr(struct intel_display *display, bool enable);
+void i9xx_wm_init(struct intel_display *display);
 #else
-static inline bool ilk_disable_cxsr(struct drm_i915_private *i915)
+static inline bool ilk_disable_cxsr(struct intel_display *display)
 {
        return false;
 }
-static inline void ilk_wm_sanitize(struct drm_i915_private *i915)
+static inline void ilk_wm_sanitize(struct intel_display *display)
 {
 }
-static inline bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable)
+static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
 {
        return false;
 }
-static inline void i9xx_wm_init(struct drm_i915_private *i915)
+static inline void i9xx_wm_init(struct intel_display *display)
 {
 }
 #endif

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 745eef470badd7bf9a9d37dfdbb403e1f94e4de1..db524d01e574d687ee76ed1444e4f873886eaf4a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -664,7 +664,6 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
                                  struct intel_plane *plane)
 {
        struct intel_display *display = to_intel_display(crtc);
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_crtc_state *crtc_state =
                to_intel_crtc_state(crtc->base.state);
        struct intel_plane_state *plane_state =
@@ -697,7 +696,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
         * wait-for-vblank between disabling the plane and the pipe.
         */
        if (HAS_GMCH(display) &&
-           intel_set_memory_cxsr(dev_priv, false))
+           intel_set_memory_cxsr(display, false))
                intel_plane_initial_vblank_wait(crtc);
 
        /*
@@ -1169,7 +1168,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
                                   struct intel_crtc *crtc)
 {
        struct intel_display *display = to_intel_display(state);
-       struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct intel_crtc_state *new_crtc_state =
@@ -1223,7 +1221,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
         * wait-for-vblank between disabling the plane and the pipe.
         */
        if (HAS_GMCH(display) && old_crtc_state->hw.active &&
-           new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
+           new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
                intel_crtc_wait_for_next_vblank(crtc);
 
        /*
@@ -1234,7 +1232,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
         * WaCxSRDisabledForSpriteScaling:ivb
         */
        if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
-           new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
+           new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
                intel_crtc_wait_for_next_vblank(crtc);
 
        /*

diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index f6d5d51dda0fb38824c83c0be8e36bba92f1c7a6..efee8925987e56fb2451c88ea3033ca4e9e8da7f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -476,7 +476,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
         * since the watermark calculation done here will use pstate->fb.
         */
        if (!HAS_GMCH(display))
-               ilk_wm_sanitize(i915);
+               ilk_wm_sanitize(display);
 
        return 0;
 

diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index 43c69a672bb34a50b819b3c48417eeebcb8442b4..bba82e888db2e12212ccd29081d4040acb9285f7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -5,8 +5,11 @@
 
 #include <linux/debugfs.h>
 
-#include "i915_drv.h"
+#include <drm/drm_file.h>
+#include <drm/drm_print.h>
+
 #include "i9xx_wm.h"
+#include "intel_display_core.h"
 #include "intel_display_types.h"
 #include "intel_wm.h"
 #include "skl_watermark.h"
@@ -169,12 +172,10 @@ void intel_print_wm_latency(struct intel_display *display,
 
 void intel_wm_init(struct intel_display *display)
 {
-       struct drm_i915_private *i915 = to_i915(display->drm);
-
        if (DISPLAY_VER(display) >= 9)
                skl_wm_init(display);
        else
-               i9xx_wm_init(i915);
+               i9xx_wm_init(display);
 }
 
 static void wm_latency_show(struct seq_file *m, const u16 wm[8])