This patch tightens mve_vector_mem_operand to reject non-register operands inside {PRE,POST}_{INC,DEC} addresses by introducing a REG_P check.
This patch fixes this ICE:https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
gcc/ChangeLog:
PR target/112337
* config/arm/arm.cc (mve_vector_mem_operand): Add a REG_P check for INC
and DEC operations.
gcc/testsuite/ChangeLog:
PR target/112337
* gcc.target/arm/mve/pr112337.c: Test for REG_P check for INC and DEC
operations.
}
code = GET_CODE (op);
- if (code == POST_INC || code == PRE_DEC
- || code == PRE_INC || code == POST_DEC)
+ if ((code == POST_INC
+ || code == PRE_DEC
+ || code == PRE_INC
+ || code == POST_DEC)
+ && REG_P (XEXP (op, 0)))
{
reg_no = arm_effective_regno (XEXP (op, 0), strict);
return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode)
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+#include <arm_mve.h>
+
+void g(int32x4_t);
+void f(int, int, int, short, int *p) {
+ int *bias = p;
+ for (;;) {
+ int32x4_t d = vldrwq_s32 (p);
+ bias += 4;
+ g(d);
+ }
+}