drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLL

Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent
updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock
Framework.  pll_7nm_register() still used in one place previous
readl+writel, which can be simplified with this new wrapper.

This is purely for readability and simplification and should have no
functional impact, because the code touched here is before clock is
registered via CCF, so there is no concurrency issue.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/638323/
Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-1-d28973fa513a@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3332399c7fd79392efeedff268a44f1a164a5326..098301880c26e6a50d919b555620578970feaa0c 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -737,11 +737,9 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
         * don't register a pclk_mux clock and just use post_out_div instead
         */
        if (pll_7nm->phy->cphy_mode) {
-               u32 data;
-
-               data = readl(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
-               writel(data | 3, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
-
+               dsi_pll_cmn_clk_cfg1_update(pll_7nm,
+                                           DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK,
+                                           DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL(3));
                phy_pll_out_dsi_parent = pll_post_out_div;
        } else {
                snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id);

diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
index 35f7f40e405b7dd9687725eae754522a7136725e..d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367 100644 (file)
--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
@@ -17,6 +17,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
                <bitfield name="CLK_EN" pos="5" type="boolean"/>
                <bitfield name="CLK_EN_SEL" pos="4" type="boolean"/>
                <bitfield name="BITCLK_SEL" low="2" high="3" type="uint"/>
+               <bitfield name="DSICLK_SEL" low="0" high="1" type="uint"/>
        </reg32>
        <reg32 offset="0x00018" name="GLBL_CTRL"/>
        <reg32 offset="0x0001c" name="RBUF_CTRL"/>