clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe

If the watchdog is part of a dedicated power domain (as it may be on
RZ/G3S) the watchdog PM domain need to be powered on in the watchdog
restart handler. Currently, only the clocks are enabled in the watchdog
restart handler. To be able to also power on the PM domain we need to
call pm_runtime_resume_and_get() on the watchdog restart handler, mark
the watchdog device as IRQ safe and register the watchdog PM domain
with GENPD_FLAG_IRQ_SAFE.

Register watchdog PM domain as IRQ safe. Along with it the always-on
PM domain (parent of the watchdog domain) was marked as IRQ safe.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index a24cafcbc619b194f4010ffe90e9cd3f83d90b22..f5f454832bb53fe8436fc1906d2024bec10cf30a 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -267,7 +267,7 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
        /* Keep always-on domain on the first position for proper domains registration. */
        DEF_PD("always-on",     R9A08G045_PD_ALWAYS_ON,
                                DEF_REG_CONF(0, 0),
-                               GENPD_FLAG_ALWAYS_ON),
+                               GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE),
        DEF_PD("gic",           R9A08G045_PD_GIC,
                                DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
                                GENPD_FLAG_ALWAYS_ON),
@@ -278,7 +278,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
                                DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
                                GENPD_FLAG_ALWAYS_ON),
        DEF_PD("wdt0",          R9A08G045_PD_WDT0,
-                               DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 0),
+                               DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
+                               GENPD_FLAG_IRQ_SAFE),
        DEF_PD("sdhi0",         R9A08G045_PD_SDHI0,
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0),
        DEF_PD("sdhi1",         R9A08G045_PD_SDHI1,