RISC-V: Enable cbo.clean/flush in usermode

Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20250226063206.71216-2-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 0ff97cf4dc2abfe11881d4ad3b88798155a78276..ef34622902bf992e4d7437da116d194387bd9216 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -32,6 +32,7 @@
 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
 
 static bool any_cpu_has_zicboz;
+static bool any_cpu_has_zicbom;
 
 unsigned long elf_hwcap __read_mostly;
 
@@ -100,6 +101,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
                pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
                return -EINVAL;
        }
+
+       any_cpu_has_zicbom = true;
        return 0;
 }
 
@@ -1036,6 +1039,11 @@ void __init riscv_user_isa_enable(void)
                current->thread.envcfg |= ENVCFG_CBZE;
        else if (any_cpu_has_zicboz)
                pr_warn("Zicboz disabled as it is unavailable on some harts\n");
+
+       if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
+               current->thread.envcfg |= ENVCFG_CBCFE;
+       else if (any_cpu_has_zicbom)
+               pr_warn("Zicbom disabled as it is unavailable on some harts\n");
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE