#define NTA_HASTYPE 1
#define NTA_HASINDEX 2
#define NTA_HASVARWIDTH 4
+#define NTA_NOINDEX 8
struct vector_type_el
{
register index.
FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
- an operand that we can be confident that it is a good match. */
+ an operand that we can be confident that it is a good match.
+
+ FLAGS includes PTR_OPTIONAL_INDEX to handle instructions with optional index
+ operands. */
#define PTR_IN_REGLIST (1U << 0)
#define PTR_FULL_REG (1U << 1)
#define PTR_GOOD_MATCH (1U << 2)
+#define PTR_OPTIONAL_INDEX (1U << 3)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.width = parsetype.width;
}
- if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
+ if ((flags & PTR_OPTIONAL_INDEX) && (*str == '\0' || *str == ','))
+ atype.defined |= NTA_NOINDEX;
+ else if ((!(flags & PTR_FULL_REG) || (flags & PTR_OPTIONAL_INDEX))
+ && skip_past_char (&str, '['))
{
/* Reject Sn[index] syntax. */
if (reg->type != REG_TYPE_Z
reg_type = REG_TYPE_Z;
goto vector_reg_index;
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
+ reg_type = REG_TYPE_Z;
+ reg = parse_typed_reg (&str, reg_type, &vectype, PTR_OPTIONAL_INDEX);
+ if (!reg || !(vectype.defined & (NTA_HASINDEX | NTA_NOINDEX)))
+ goto failure;
+ goto vector_reg_optional_index;
+
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
goto failure;
if (!(vectype.defined & NTA_HASINDEX))
goto failure;
-
+ vector_reg_optional_index:
if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype)
/* Unqualified Zn[index] is allowed in LUTI2 instructions. */
info->qualifier = AARCH64_OPND_QLF_NIL;
--- /dev/null
+#name: Test of illegal pmov instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-7-invalid.l
--- /dev/null
+.*: Assembler messages:
+.*: Error: operand mismatch -- `pmov p0,z0'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.b,z0'
+.*: Error: register element index must be 0 at operand 2 -- `pmov p0.b,z31\[1\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov p15,z31.b\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7,z15.b'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7,w15.b'
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7.b,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[3\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[3\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.h,z0'
+.*: Error: register element index out of range 0 to 1 at operand 2 -- `pmov p0.h,z31\[2\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov p15,z31.h\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7.h,z15.h'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,x15.h'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,w15'
+.*: Error: operand mismatch -- `pmov p0,z0\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[4\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.s,z0'
+.*: Error: register element index out of range 0 to 3 at operand 2 -- `pmov p0.s,z31\[5\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov p15,z31.s\[6\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[6\]
+.*: Error: operand mismatch -- `pmov p7.s,z15.s'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.s, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,w15.s'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[8\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[8\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.d,z0'
+.*: Error: register element index out of range 0 to 7 at operand 2 -- `pmov p0.d,z31\[10\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov p15,z31.d\[12\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[12\]
+.*: Error: operand mismatch -- `pmov p7.d,z15.d'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.d, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,x15.d'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,w15'
+.*: Error: operand mismatch -- `pmov z0,p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0, p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.b'
+.*: Error: register element index must be 0 at operand 1 -- `pmov z31\[1\],p0.b'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov z31.b\[4\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[4\], p15.b
+.*: Error: operand mismatch -- `pmov z15.b,p7.b'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x15.b,p7.b'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w15.b,p7'
+.*: Error: operand mismatch -- `pmov z0\[3\],p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0\[3\], p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.h'
+.*: Error: register element index out of range 0 to 1 at operand 1 -- `pmov z31\[2\],p0.h'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov z31.h\[5\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[5\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.h,p7.h'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.h
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.h,p7.h'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.h,p7'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z0\[5\],p0.s'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.s'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z31\[6\],p0.s'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov z31.s\[7\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[7\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.s,p7.s'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.s
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.s,p7.s'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.s,p7'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z0\[8\],p0.d'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.d'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z31\[9\],p0.d'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov z31.d\[10\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[10\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.d,p7.d'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.d
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.d,p7.d'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.d,p7'
--- /dev/null
+/* PMOV (to predicate). */
+pmov p0, z0
+pmov p16.b, z0
+pmov p0.b, z31[1]
+pmov p15.b
+pmov p15, z31.b[4]
+pmov p7, z15.b
+mov p7, w15.b
+mov p7.b, x15
+
+pmov p0, z0[3]
+pmov p16.h, z0
+pmov p0.h, z31[2]
+pmov p15.h
+pmov p15, z31.h[4]
+pmov p7.h, z15.h
+pmov p7.h, x15.h
+pmov p7.h, w15
+
+pmov p0, z0[4]
+pmov p16.s, z0
+pmov p0.s, z31[5]
+pmov p15.s
+pmov p15, z31.s[6]
+pmov p7.s, z15.s
+pmov p7.s, w15.s
+pmov p7.s, x15
+
+pmov p0, z0[8]
+pmov p16.d, z0
+pmov p0.d, z31[10]
+pmov p15.d
+pmov p15, z31.d[12]
+pmov p7.d, z15.d
+pmov p7.d, x15.d
+pmov p7.d, w15
+
+/* PMOV (to vector). */
+pmov z0, p0
+pmov z0, p16.b
+pmov z31[1], p0.b
+pmov p15.b
+pmov z31.b[4], p15
+pmov z15.b, p7.b
+pmov x15.b, p7.b
+pmov w15.b, p7
+
+pmov z0[3], p0
+pmov z0, p16.h
+pmov z31[2], p0.h
+pmov p15.h
+pmov z31.h[5], p15
+pmov z15, p7
+pmov z8.h, p7.h
+pmov x8.h, p7.h
+pmov w8.h, p7
+
+pmov z0[5], p0.s
+pmov z0, p16.s
+pmov z31[6], p0.s
+pmov p15.s
+pmov z31.s[7], p15
+pmov z15, p7
+pmov z8.s, p7.s
+pmov x8.s, p7.s
+pmov w8.s, p7
+
+pmov z0[8], p0.d
+pmov z0, p16.d
+pmov z31[9], p0.d
+pmov p15.d
+pmov z31.d[10], p15
+pmov z15, p7
+pmov z8.d, p7.d
+pmov w8.d, p7.d
+pmov x8.d, p7
--- /dev/null
+#name: Test of SVE2.1 pmov instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 052a3800 pmov p0.b, z0
+.*: 052a380f pmov p15.b, z0
+.*: 052a3be0 pmov p0.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a39e7 pmov p7.b, z15
+.*: 052c3800 pmov p0.h, z0
+.*: 052c380f pmov p15.h, z0
+.*: 052c3be0 pmov p0.h, z31
+.*: 052e3800 pmov p0.h, z0\[1\]
+.*: 052e3bef pmov p15.h, z31\[1\]
+.*: 052c39e7 pmov p7.h, z15
+.*: 052c3903 pmov p3.h, z8
+.*: 05683800 pmov p0.s, z0
+.*: 0568380f pmov p15.s, z0
+.*: 05683be0 pmov p0.s, z31
+.*: 056e3800 pmov p0.s, z0\[3\]
+.*: 056e3bef pmov p15.s, z31\[3\]
+.*: 056a39e7 pmov p7.s, z15\[1\]
+.*: 05683903 pmov p3.s, z8
+.*: 05a83800 pmov p0.d, z0
+.*: 05a8380f pmov p15.d, z0
+.*: 05a83be0 pmov p0.d, z31
+.*: 05ee3800 pmov p0.d, z0\[7\]
+.*: 05ee3bef pmov p15.d, z31\[7\]
+.*: 05ae39e7 pmov p7.d, z15\[3\]
+.*: 05a83903 pmov p3.d, z8
+.*: 052b3800 pmov z0, p0.b
+.*: 052b381f pmov z31, p0.b
+.*: 052b39e0 pmov z0, p15.b
+.*: 052b39ff pmov z31, p15.b
+.*: 052b38e0 pmov z0, p7.b
+.*: 052b38ef pmov z15, p7.b
+.*: 052d3800 pmov z0, p0.h
+.*: 052d381f pmov z31, p0.h
+.*: 052f3800 pmov z0\[1\], p0.h
+.*: 052d39e0 pmov z0, p15.h
+.*: 052f39ff pmov z31\[1\], p15.h
+.*: 052d39ef pmov z15, p15.h
+.*: 052d38e8 pmov z8, p7.h
+.*: 05693800 pmov z0, p0.s
+.*: 0569381f pmov z31, p0.s
+.*: 056f3800 pmov z0\[3\], p0.s
+.*: 056939e0 pmov z0, p15.s
+.*: 056f39ff pmov z31\[3\], p15.s
+.*: 056d39ef pmov z15\[2\], p15.s
+.*: 056938e8 pmov z8, p7.s
+.*: 05a93800 pmov z0, p0.d
+.*: 05a9381f pmov z31, p0.d
+.*: 05ef3800 pmov z0\[7\], p0.d
+.*: 05a939e0 pmov z0, p15.d
+.*: 05ef39ff pmov z31\[7\], p15.d
+.*: 05af39ef pmov z15\[3\], p15.d
+.*: 05a938e8 pmov z8, p7.d
--- /dev/null
+/* PMOV (to predicate). */
+pmov p0.b, z0
+pmov p15.b, z0
+pmov p0.b, z31
+pmov p15.b, z31
+pmov p15.b, z31[0]
+pmov p7.b, z15
+
+pmov p0.h, z0[0]
+pmov p15.h, z0[0]
+pmov p0.h, z31[0]
+pmov p0.h, z0[1]
+pmov p15.h, z31[1]
+pmov p7.h, z15[0]
+pmov p3.h, z8
+
+pmov p0.s, z0[0]
+pmov p15.s, z0[0]
+pmov p0.s, z31[0]
+pmov p0.s, z0[3]
+pmov p15.s, z31[3]
+pmov p7.s, z15[1]
+pmov p3.s, z8
+
+pmov p0.d, z0[0]
+pmov p15.d, z0[0]
+pmov p0.d, z31[0]
+pmov p0.d, z0[7]
+pmov p15.d, z31[7]
+pmov p7.d, z15[3]
+pmov p3.d, z8
+
+/* PMOV (to vector). */
+pmov z0, p0.b
+pmov z31, p0.b
+pmov z0, p15.b
+pmov z31, p15.b
+pmov z0[0], p7.b
+pmov z15[0], p7.b
+
+pmov z0[0], p0.h
+pmov z31[0], p0.h
+pmov z0[1], p0.h
+pmov z0[0], p15.h
+pmov z31[1], p15.h
+pmov z15[0], p15.h
+pmov z8, p7.h
+
+pmov z0[0], p0.s
+pmov z31[0], p0.s
+pmov z0[3], p0.s
+pmov z0[0], p15.s
+pmov z31[3], p15.s
+pmov z15[2], p15.s
+pmov z8, p7.s
+
+pmov z0[0], p0.d
+pmov z31[0], p0.d
+pmov z0[7], p0.d
+pmov z0[0], p15.d
+pmov z31[7], p15.d
+pmov z15[3], p15.d
+pmov z8, p7.d
AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
+ AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
+ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
+ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
+ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
+ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
+ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
+ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
+ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
case 267:
case 268:
case 269:
+ case 303:
+ case 307:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 305:
- case 308:
+ case 313:
+ case 316:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 37:
case 38:
case 39:
- case 310:
+ case 318:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
case 300:
case 301:
case 302:
+ case 304:
+ case 305:
+ case 306:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 211:
case 212:
case 272:
- case 303:
- case 304:
- case 306:
- case 307:
- case 309:
+ case 311:
+ case 312:
case 314:
case 315:
+ case 317:
+ case 322:
+ case 323:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 284:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 311:
- case 312:
- case 313:
- return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 316:
- case 317:
- case 318:
case 319:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 320:
+ case 321:
+ return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
+ case 325:
+ case 326:
+ case 327:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 328:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3401;
+ return 3409;
}
else
{
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3402;
+ return 3410;
}
}
}
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3403;
+ return 3411;
}
}
else
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3469;
+ return 3477;
}
else
{
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3468;
+ return 3476;
}
}
else
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3462;
+ return 3470;
}
}
}
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3447;
+ return 3455;
}
}
else
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3461;
+ return 3469;
}
}
}
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3454;
+ return 3462;
}
}
}
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3453;
+ return 3461;
}
}
}
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3460;
+ return 3468;
}
else
{
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3440;
+ return 3448;
}
else
{
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3441;
+ return 3449;
}
else
{
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3452;
+ return 3460;
}
else
{
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3471;
+ return 3479;
}
else
{
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3446;
+ return 3454;
}
}
}
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3470;
+ return 3478;
}
}
}
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3472;
+ return 3480;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3466;
+ return 3474;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3467;
+ return 3475;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3464;
+ return 3472;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3465;
+ return 3473;
}
}
}
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3450;
+ return 3458;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3451;
+ return 3459;
}
}
}
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3458;
+ return 3466;
}
else
{
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3459;
+ return 3467;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3456;
+ return 3464;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3457;
+ return 3465;
}
}
}
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3463;
+ return 3471;
}
}
else
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3455;
+ return 3463;
}
}
else
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3404;
+ return 3412;
}
}
else
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3405;
+ return 3413;
}
}
}
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3444;
+ return 3452;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3445;
+ return 3453;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3448;
+ return 3456;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3449;
+ return 3457;
}
}
}
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3406;
+ return 3414;
}
}
else
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3407;
+ return 3415;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3442;
+ return 3450;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3443;
+ return 3451;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3378;
+ return 3386;
}
}
else
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3375;
+ return 3383;
}
else
{
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3370;
+ return 3378;
}
}
else
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3376;
+ return 3384;
}
}
else
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3377;
+ return 3385;
}
}
}
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3371;
+ return 3379;
}
else
{
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3372;
+ return 3380;
}
}
else
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3366;
+ return 3374;
}
else
{
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3367;
+ return 3375;
}
}
}
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3373;
+ return 3381;
}
else
{
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3374;
+ return 3382;
}
}
else
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3368;
+ return 3376;
}
else
{
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3369;
+ return 3377;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3380;
+ return 3388;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3379;
+ return 3387;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3381;
+ return 3389;
}
}
}
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3382;
+ return 3390;
}
else
{
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3383;
+ return 3391;
}
}
}
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3384;
+ return 3392;
}
else
{
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3385;
+ return 3393;
}
}
}
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3386;
+ return 3394;
}
else
{
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3388;
+ return 3396;
}
else
{
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3387;
+ return 3395;
}
else
{
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3389;
+ return 3397;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3391;
+ return 3399;
}
}
else
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3390;
+ return 3398;
}
}
}
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3327;
+ return 3335;
}
else
{
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3336;
+ return 3344;
}
else
{
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3335;
+ return 3343;
}
else
{
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3337;
+ return 3345;
}
}
}
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3328;
+ return 3336;
}
}
}
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3331;
+ return 3339;
}
}
else
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3338;
+ return 3346;
}
}
else
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3339;
+ return 3347;
}
}
else
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3340;
+ return 3348;
}
}
}
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3427;
+ return 3435;
}
}
else
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3429;
+ return 3437;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3439;
+ return 3447;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3425;
+ return 3433;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3430;
+ return 3438;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3426;
+ return 3434;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3431;
+ return 3439;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3432;
+ return 3440;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3428;
+ return 3436;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3435;
+ return 3443;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3438;
+ return 3446;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3424;
+ return 3432;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3433;
+ return 3441;
}
}
else
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3437;
+ return 3445;
}
}
else
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3334;
+ return 3342;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3434;
+ return 3442;
}
else
{
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3436;
+ return 3444;
}
}
else
{
if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1x1000001110xxxxxxxxxx
- rev. */
- return 1869;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx100100001110xxxxxxxxxx
+ insr. */
+ return 1559;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx110100001110xxxxxxxxxx
+ insr. */
+ return 1560;
+ }
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x10001110xxxxxxxxxx
+ uunpklo. */
+ return 2080;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx10x100001110xxxxxxxxxx
- insr. */
- return 1559;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001010x0001110xxxxxxxxxx
+ pmov. */
+ return 3327;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001011x0001110xxxxxxxxxx
+ pmov. */
+ return 3328;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x101101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3329;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 000001x1xx11x100001110xxxxxxxxxx
- insr. */
- return 1560;
+ 000001x11x101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3330;
}
}
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx10001110xxxxxxxxxx
- uunpklo. */
- return 2080;
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx111xx0001110xxxxxxxxxx
+ rev. */
+ return 1869;
+ }
}
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx01001110xxxxxxxxxx
- sunpkhi. */
- return 2016;
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x01001110xxxxxxxxxx
+ sunpkhi. */
+ return 2016;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x11001110xxxxxxxxxx
+ uunpkhi. */
+ return 2079;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx11001110xxxxxxxxxx
- uunpkhi. */
- return 2079;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x10x1001110xxxxxxxxxx
+ pmov. */
+ return 3331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x11x1001110xxxxxxxxxx
+ pmov. */
+ return 3332;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1011x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3333;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x11x1x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3334;
+ }
}
}
}
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3396;
+ return 3404;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3397;
+ return 3405;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3398;
+ return 3406;
}
else
{
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3399;
+ return 3407;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3400;
+ return 3408;
}
}
}
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3358;
+ return 3366;
}
else
{
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3354;
+ return 3362;
}
}
else
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3359;
+ return 3367;
}
else
{
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3355;
+ return 3363;
}
}
}
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3363;
+ return 3371;
}
else
{
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3362;
+ return 3370;
}
}
else
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3364;
+ return 3372;
}
else
{
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3365;
+ return 3373;
}
}
}
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3360;
+ return 3368;
}
else
{
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3356;
+ return 3364;
}
}
else
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3361;
+ return 3369;
}
else
{
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3357;
+ return 3365;
}
}
}
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3329;
+ return 3337;
}
else
{
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3330;
+ return 3338;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3332;
+ return 3340;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3333;
+ return 3341;
}
}
else
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3392;
+ return 3400;
}
}
}
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3394;
+ return 3402;
}
else
{
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3395;
+ return 3403;
}
}
else
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3393;
+ return 3401;
}
}
}
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3416;
+ return 3424;
}
else
{
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3418;
+ return 3426;
}
}
else
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3417;
+ return 3425;
}
else
{
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3419;
+ return 3427;
}
}
}
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3349;
+ return 3357;
}
else
{
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3350;
+ return 3358;
}
}
else
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3351;
+ return 3359;
}
}
}
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3408;
+ return 3416;
}
else
{
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3410;
+ return 3418;
}
else
{
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3412;
+ return 3420;
}
else
{
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3413;
+ return 3421;
}
}
}
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3352;
+ return 3360;
}
}
}
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3345;
+ return 3353;
}
else
{
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3346;
+ return 3354;
}
}
else
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3341;
+ return 3349;
}
else
{
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3342;
+ return 3350;
}
}
}
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3347;
+ return 3355;
}
else
{
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3348;
+ return 3356;
}
}
else
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3343;
+ return 3351;
}
else
{
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3344;
+ return 3352;
}
}
}
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3353;
+ return 3361;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3409;
+ return 3417;
}
else
{
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3411;
+ return 3419;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3414;
+ return 3422;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3415;
+ return 3423;
}
}
}
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3420;
+ return 3428;
}
else
{
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3422;
+ return 3430;
}
}
else
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3421;
+ return 3429;
}
else
{
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3423;
+ return 3431;
}
}
}
case 267:
case 268:
case 269:
+ case 303:
+ case 307:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 305:
- case 308:
+ case 313:
+ case 316:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 37:
case 38:
case 39:
- case 310:
+ case 318:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
case 300:
case 301:
case 302:
+ case 304:
+ case 305:
+ case 306:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 211:
case 212:
case 272:
- case 303:
- case 304:
- case 306:
- case 307:
- case 309:
+ case 311:
+ case 312:
case 314:
case 315:
+ case 317:
+ case 322:
+ case 323:
return aarch64_ext_imm (self, info, code, inst, errors);
case 52:
case 53:
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
case 284:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 311:
- case 312:
- case 313:
- return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
- case 316:
- case 317:
- case 318:
case 319:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 320:
+ case 321:
+ return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
+ case 325:
+ case 326:
+ case 327:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 328:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_1}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_2}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_1}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_2}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
{ 5, 14 }, /* imm14: in test bit and branch instructions. */
{ 0, 16 }, /* imm16_0: in udf instruction. */
{ 5, 16 }, /* imm16_5: in exception instructions. */
+ { 17, 1 }, /* imm17_1: in 1 bit element index. */
+ { 17, 2 }, /* imm17_2: in 2 bits element index. */
{ 5, 19 }, /* imm19: e.g. in CBZ. */
{ 0, 26 }, /* imm26: in unconditional branch instructions. */
{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
case AARCH64_OPND_SME_Zn_INDEX3_14:
case AARCH64_OPND_SME_Zn_INDEX3_15:
case AARCH64_OPND_SME_Zn_INDEX4_14:
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
size = get_operand_fields_width (get_operand_from_code (type)) - 5;
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
0, (1 << size) - 1))
case AARCH64_OPND_SVE_Zt:
case AARCH64_OPND_SME_Zm:
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
- snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
+ snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
else
- snprintf (buf, size, "%s",
- style_reg (styler, "z%d.%s", opnd->reg.regno,
- aarch64_get_qualifier_name (opnd->qualifier)));
+ snprintf (buf, size, "%s",
+ style_reg (styler, "z%d.%s", opnd->reg.regno,
+ aarch64_get_qualifier_name (opnd->qualifier)));
break;
case AARCH64_OPND_SVE_ZnxN:
style_imm (styler, "%" PRIi64, opnd->reglane.index));
break;
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
+ if (opnd->reglane.index == 0)
+ snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
+ else
+ snprintf (buf, size, "%s[%s]",
+ style_reg (styler, "z%d", opnd->reglane.regno),
+ style_imm (styler, "%" PRIi64, opnd->reglane.index));
+ break;
+
case AARCH64_OPND_SME_ZAda_1b:
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
FLD_imm14,
FLD_imm16_0,
FLD_imm16_5,
+ FLD_imm17_1,
+ FLD_imm17_2,
FLD_imm19,
FLD_imm26,
FLD_immb,
QLF3(S_B,P_Z,S_B), \
QLF3(S_B,P_M,S_B), \
}
+#define OP_SVE_BU \
+{ \
+ QLF2(S_B,NIL), \
+}
#define OP_SVE_BUB \
{ \
QLF3(S_B,NIL,S_B), \
{ \
QLF3(S_S,P_Z,NIL), \
}
-#define OP_SVE_UB \
-{ \
- QLF2(NIL,S_B), \
+#define OP_SVE_UB \
+{ \
+ QLF2(NIL,S_B), \
+}
+#define OP_SVE_UD \
+{ \
+ QLF2(NIL,S_D), \
+}
+#define OP_SVE_UH \
+{ \
+ QLF2(NIL,S_H), \
+}
+#define OP_SVE_US \
+{ \
+ QLF2(NIL,S_S), \
}
#define OP_SVE_UUD \
{ \
SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_INSN("pmov",0x052a3800, 0xfffffc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn0_INDEX), OP_SVE_BU, 0, 0),
+ SVE2p1_INSN("pmov",0x052c3800, 0xfffdfc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn1_17_INDEX), OP_SVE_HU, 0, 0),
+ SVE2p1_INSN("pmov",0x05683800, 0xfff9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn2_18_INDEX), OP_SVE_SU, 0, 0),
+ SVE2p1_INSN("pmov",0x05a83800, 0xffb9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn3_22_INDEX), OP_SVE_DU, 0, 0),
+
+ SVE2p1_INSN("pmov",0x052b3800, 0xfffffe00, sve_misc, 0, OP2 (SVE_Zd0_INDEX, SVE_Pg4_5), OP_SVE_UB, 0, 0),
+ SVE2p1_INSN("pmov",0x052d3800, 0xfffdfe00, sve_misc, 0, OP2 (SVE_Zd1_17_INDEX, SVE_Pg4_5), OP_SVE_UH, 0, 0),
+ SVE2p1_INSN("pmov",0x05693800, 0xfff9fe00, sve_misc, 0, OP2 (SVE_Zd2_18_INDEX, SVE_Pg4_5), OP_SVE_US, 0, 0),
+ SVE2p1_INSN("pmov",0x05a93800, 0xffb9fe00, sve_misc, 0, OP2 (SVE_Zd3_22_INDEX, SVE_Pg4_5), OP_SVE_UD, 0, 0),
+
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0),
F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \
F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \
+ Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD_SVE_Zn), \
+ "an SVE vector register with option zero index") \
+ Y(SVE_REG, simple_index, "SVE_Zn1_17_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_imm17_1), \
+ "an SVE vector register with optional one bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zn2_18_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_imm17_2), \
+ "an SVE vector register with optional two bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zn3_22_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2), \
+ "an SVE vector register with optional three bit index") \
+ Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD_SVE_Zd), \
+ "an SVE vector register with option zero index") \
+ Y(SVE_REG, simple_index, "SVE_Zd1_17_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_imm17_1), \
+ "an SVE vector register with optional one bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zd2_18_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_imm17_2), \
+ "an SVE vector register with optional two bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zd3_22_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2), \
+ "an SVE vector register with optional three bit index") \
Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \
"VLx2 or VLx4") \
Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \
projects / thirdparty / binutils-gdb.git / commitdiff
