]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.15-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 15 Apr 2023 07:00:07 +0000 (09:00 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 15 Apr 2023 07:00:07 +0000 (09:00 +0200)
added patches:
revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch
series

queue-5.15/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch [new file with mode: 0644]
queue-5.15/series [new file with mode: 0644]

diff --git a/queue-5.15/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch b/queue-5.15/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch
new file mode 100644 (file)
index 0000000..9aefd19
--- /dev/null
@@ -0,0 +1,91 @@
+From 534e465845ebfb4a97eb5459d3931a0b35e3b9a5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= <korneld@chromium.org>
+Date: Tue, 11 Apr 2023 13:49:32 +0000
+Subject: Revert "pinctrl: amd: Disable and mask interrupts on resume"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Kornel Dulęba <korneld@chromium.org>
+
+commit 534e465845ebfb4a97eb5459d3931a0b35e3b9a5 upstream.
+
+This reverts commit b26cd9325be4c1fcd331b77f10acb627c560d4d7.
+
+This patch introduces a regression on Lenovo Z13, which can't wake
+from the lid with it applied; and some unspecified AMD based Dell
+platforms are unable to wake from hitting the power button
+
+Signed-off-by: Kornel Dulęba <korneld@chromium.org>
+Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
+Link: https://lore.kernel.org/r/20230411134932.292287-1-korneld@chromium.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/pinctrl-amd.c |   36 ++++++++++++++++--------------------
+ 1 file changed, 16 insertions(+), 20 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-amd.c
++++ b/drivers/pinctrl/pinctrl-amd.c
+@@ -863,34 +863,32 @@ static const struct pinconf_ops amd_pinc
+       .pin_config_group_set = amd_pinconf_group_set,
+ };
+-static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin)
++static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
+ {
+-      const struct pin_desc *pd;
++      struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+       unsigned long flags;
+       u32 pin_reg, mask;
++      int i;
+       mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
+               BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
+               BIT(WAKE_CNTRL_OFF_S4);
+-      pd = pin_desc_get(gpio_dev->pctrl, pin);
+-      if (!pd)
+-              return;
++      for (i = 0; i < desc->npins; i++) {
++              int pin = desc->pins[i].number;
++              const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
+-      raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+-      pin_reg = readl(gpio_dev->base + pin * 4);
+-      pin_reg &= ~mask;
+-      writel(pin_reg, gpio_dev->base + pin * 4);
+-      raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+-}
++              if (!pd)
++                      continue;
+-static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
+-{
+-      struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+-      int i;
++              raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+-      for (i = 0; i < desc->npins; i++)
+-              amd_gpio_irq_init_pin(gpio_dev, i);
++              pin_reg = readl(gpio_dev->base + i * 4);
++              pin_reg &= ~mask;
++              writel(pin_reg, gpio_dev->base + i * 4);
++
++              raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
++      }
+ }
+ #ifdef CONFIG_PM_SLEEP
+@@ -943,10 +941,8 @@ static int amd_gpio_resume(struct device
+       for (i = 0; i < desc->npins; i++) {
+               int pin = desc->pins[i].number;
+-              if (!amd_gpio_should_save(gpio_dev, pin)) {
+-                      amd_gpio_irq_init_pin(gpio_dev, pin);
++              if (!amd_gpio_should_save(gpio_dev, pin))
+                       continue;
+-              }
+               raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+               gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
diff --git a/queue-5.15/series b/queue-5.15/series
new file mode 100644 (file)
index 0000000..e1c2c0b
--- /dev/null
@@ -0,0 +1 @@
+revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch