ARM: soft-fp NaN representation correction

Commit 7d92b78723848ae616709eb8f0191ea067025b18 [Fix ARM NAN fraction
bits.] removed all the bits set from NANFRAC macros and, when propagated
to libgcc, regressed gcc.dg/torture/builtin-math-7.c on soft-fp arm-eabi
targets, currently ARMv6-M (`-march=armv6-m -mthumb') only.  This is
because when used to construct a NaN in the semi-raw mode, they now
build an infinity instead.  Consequently operations such as (Inf - Inf)
now produce Inf rather than NaN.  The change worked for the original
test case, posted with PR libgcc/60166, because division is made in the
canonical mode, where the quiet bit is set separately, from the fp
class.

This change brings the quiet bit back to these macros, making semi-raw
mode calculations produce the expected results again.

diff --git a/ChangeLog b/ChangeLog
index 6a6881d85eae2c8ea3c8bc36296becd5ce377f16..6e913efa87c3c00d11abeea2d7bf988ec4171eb4 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2014-05-16  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       PR libgcc/60166
+       * sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D)
+       (_FP_NANSIGN_Q): Set the quiet bit.
+
 2014-05-16  Joseph Myers  <joseph@codesourcery.com>
 
        * benchtests/Makefile

diff --git a/sysdeps/arm/soft-fp/sfp-machine.h b/sysdeps/arm/soft-fp/sfp-machine.h
index 32697fef44ad208284f0363674e1411ab7965516..2e7c1562941065d42e3233b9dc62293bf4662294 100644 (file)
--- a/sysdeps/arm/soft-fp/sfp-machine.h
+++ b/sysdeps/arm/soft-fp/sfp-machine.h
@@ -21,9 +21,9 @@
 #define _FP_DIV_MEAT_D(R,X,Y)  _FP_DIV_MEAT_2_udiv(D,R,X,Y)
 #define _FP_DIV_MEAT_Q(R,X,Y)  _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
 
-#define _FP_NANFRAC_S          0
-#define _FP_NANFRAC_D          0, 0
-#define _FP_NANFRAC_Q          0, 0, 0, 0
+#define _FP_NANFRAC_S          _FP_QNANBIT_S
+#define _FP_NANFRAC_D          _FP_QNANBIT_D, 0
+#define _FP_NANFRAC_Q          _FP_QNANBIT_Q, 0, 0, 0
 #define _FP_NANSIGN_S          0
 #define _FP_NANSIGN_D          0
 #define _FP_NANSIGN_Q          0