]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
Fix PR 106690: enable effective_target_bswap for RISCV targets with ZBB enabled by...
authorAndrew Pinski <apinski@marvell.com>
Fri, 19 Aug 2022 22:09:30 +0000 (22:09 +0000)
committerAndrew Pinski <apinski@marvell.com>
Wed, 24 Aug 2022 18:30:51 +0000 (11:30 -0700)
While looking for testcases to quickly test, I Noticed that
check_effective_target_bswap was not enabled for riscv when
ZBB is enabled. This patch checks if ZBB is enabled when
targeting RISCV* for bswap.

OK? Ran the testsuite for riscv32-linux-gnu both with and without ZBB enabled.

PR testsuite/106690
gcc/testsuite/ChangeLog:

* lib/target-supports.exp (check_effective_target_bswap):
Return true if riscv and ZBB ISA extension is enabled.

gcc/testsuite/lib/target-supports.exp

index 04a2a8e8659d05f8405be9e22e8bb406df8089ca..0f1e1af31e9c3825e787f63a7873c33c7b253f6f 100644 (file)
@@ -8646,6 +8646,13 @@ proc check_effective_target_bswap { } {
             || [istarget powerpc*-*-*]
             || [istarget rs6000-*-*]
             || [istarget s390*-*-*]
+            || ([istarget riscv*-*-*]
+                && [check_no_compiler_messages_nocache riscv_zbb object {
+                    #if __riscv_zbb  <= 0
+                    #error ZBB is not enabled
+                    #endif
+                    int i;
+                } ""])
             || ([istarget arm*-*-*]
                 && [check_no_compiler_messages_nocache arm_v6_or_later object {
                     #if __ARM_ARCH < 6