--- /dev/null
+From 84c63d040938f64a7dc195696301166e75231bf5 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 6 May 2021 22:46:52 -0400
+Subject: drm/amd/display: Use the correct max downscaling value for DCN3.x family
+
+From: Nikola Cornij <nikola.cornij@amd.com>
+
+commit 84c63d040938f64a7dc195696301166e75231bf5 upstream.
+
+[why]
+As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The
+max downscaling limit value for DCN2.x is 250, which means it's
+calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167.
+
+[how]
+Set maximum downscaling limit to 167 for DCN3.x
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Stylon Wang <stylon.wang@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 7 ++++---
+ drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 7 ++++---
+ drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 7 ++++---
+ 3 files changed, 12 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+@@ -826,10 +826,11 @@ static const struct dc_plane_cap plane_c
+ .fp16 = 16000
+ },
+
++ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
+ .max_downscale_factor = {
+- .argb8888 = 600,
+- .nv12 = 600,
+- .fp16 = 600
++ .argb8888 = 167,
++ .nv12 = 167,
++ .fp16 = 167
+ }
+ };
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+@@ -843,10 +843,11 @@ static const struct dc_plane_cap plane_c
+ .fp16 = 16000
+ },
+
++ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
+ .max_downscale_factor = {
+- .argb8888 = 600,
+- .nv12 = 600,
+- .fp16 = 600
++ .argb8888 = 167,
++ .nv12 = 167,
++ .fp16 = 167
+ },
+ 64,
+ 64
+--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+@@ -282,10 +282,11 @@ static const struct dc_plane_cap plane_c
+ .nv12 = 16000,
+ .fp16 = 16000
+ },
++ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
+ .max_downscale_factor = {
+- .argb8888 = 600,
+- .nv12 = 600,
+- .fp16 = 600
++ .argb8888 = 167,
++ .nv12 = 167,
++ .fp16 = 167
+ },
+ 16,
+ 16
--- /dev/null
+From 036867e93ebf4d7e70eba6a8c72db74ee3760bc3 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Mon, 17 May 2021 09:46:40 +0100
+Subject: drm/i915/gem: Pin the L-shape quirked object as unshrinkable
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 036867e93ebf4d7e70eba6a8c72db74ee3760bc3 upstream.
+
+When instantiating a tiled object on an L-shaped memory machine, we mark
+the object as unshrinkable to prevent the shrinker from trying to swap
+out the pages. We have to do this as we do not know the swizzling on the
+individual pages, and so the data will be scrambled across swap out/in.
+
+Not only do we need to move the object off the shrinker list, we need to
+mark the object with shrink_pin so that the counter is consistent across
+calls to madvise.
+
+v2: in the madvise ioctl we need to check if the object is currently
+shrinkable/purgeable, not if the object type supports shrinking
+
+Fixes: 0175969e489a ("drm/i915/gem: Use shrinkable status for unknown swizzle quirks")
+References: https://gitlab.freedesktop.org/drm/intel/-/issues/3293
+References: https://gitlab.freedesktop.org/drm/intel/-/issues/3450
+Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Matthew Auld <matthew.auld@intel.com>
+Signed-off-by: Matthew Auld <matthew.auld@intel.com>
+Cc: <stable@vger.kernel.org> # v5.12+
+Link: https://patchwork.freedesktop.org/patch/msgid/20210517084640.18862-1-matthew.auld@intel.com
+(cherry picked from commit 8777d17b68dcfbfbd4d524f444adefae56f41225)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 ++
+ drivers/gpu/drm/i915/i915_gem.c | 11 +++++------
+ 2 files changed, 7 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
++++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+@@ -63,6 +63,8 @@ void __i915_gem_object_set_pages(struct
+ i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
+ i915_gem_object_set_tiling_quirk(obj);
++ GEM_BUG_ON(!list_empty(&obj->mm.link));
++ atomic_inc(&obj->mm.shrink_pin);
+ shrinkable = false;
+ }
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -972,12 +972,11 @@ i915_gem_madvise_ioctl(struct drm_device
+ obj->mm.madv = args->madv;
+
+ if (i915_gem_object_has_pages(obj)) {
+- struct list_head *list;
++ unsigned long flags;
+
+- if (i915_gem_object_is_shrinkable(obj)) {
+- unsigned long flags;
+-
+- spin_lock_irqsave(&i915->mm.obj_lock, flags);
++ spin_lock_irqsave(&i915->mm.obj_lock, flags);
++ if (!list_empty(&obj->mm.link)) {
++ struct list_head *list;
+
+ if (obj->mm.madv != I915_MADV_WILLNEED)
+ list = &i915->mm.purge_list;
+@@ -985,8 +984,8 @@ i915_gem_madvise_ioctl(struct drm_device
+ list = &i915->mm.shrink_list;
+ list_move_tail(&obj->mm.link, list);
+
+- spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
+ }
++ spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
+ }
+
+ /* if the object is no longer attached, discard its backing storage */
projects / thirdparty / kernel / stable-queue.git / commitdiff
