revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"

This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The
specification is going to by updated in a way rendering this change
wrong.

diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s
index b3eb7b0ceca9f3e288fb67772b2ad1ab3acb24f0..63bc6c1352c2ea14f8736c4f5f4a97631df3f5e2 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-user_msr.s
+++ b/gas/testsuite/gas/i386/x86-64-user_msr.s
@@ -5,7 +5,7 @@ _start:
        urdmsr  %r14, %r12
        urdmsr  %r14, %rax
        urdmsr  %rdx, %r12
-       urdmsr  %edx, %rax
+       urdmsr  %rdx, %rax
        urdmsr  $51515151, %r12
        urdmsr  $51515151, %rax
        urdmsr  $0x7f, %r12
@@ -14,7 +14,7 @@ _start:
        uwrmsr  %r12, %r14
        uwrmsr  %rax, %r14
        uwrmsr  %r12, %rdx
-       uwrmsr  %rax, %edx
+       uwrmsr  %rax, %rdx
        uwrmsr  %r12, $51515151
        uwrmsr  %rax, $51515151
        uwrmsr  %r12, $0x7f
@@ -24,7 +24,7 @@ _start:
        .intel_syntax noprefix
        urdmsr  r12, r14
        urdmsr  rax, r14
-       urdmsr  r12, edx
+       urdmsr  r12, rdx
        urdmsr  rax, rdx
        urdmsr  r12, 51515151
        urdmsr  rax, 51515151
@@ -33,7 +33,7 @@ _start:
        urdmsr  r12, 0x80000000
        uwrmsr  r14, r12
        uwrmsr  r14, rax
-       uwrmsr  edx, r12
+       uwrmsr  rdx, r12
        uwrmsr  rdx, rax
        uwrmsr  51515151, r12
        uwrmsr  51515151, rax

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index eaa79adacebd1c63d27dd1f6422704051d36e988..fffe05d4399fafcb4eff0a293b7a85b57677764e 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3359,9 +3359,9 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
 
 // USER_MSR instructions.
 
-urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg32|Reg64, Reg64 }
+urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
 urdmsr, 0xf2f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
-uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg32|Reg64 }
+uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
 // Immediates want to be first; md_assemble() takes care of swapping operands
 // accordingly.
 uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 024d194b06a9ebdb0302118e97563465828d6254..c4347d40f8e0d20695e61fefd68a600e5c86ad08 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -35866,7 +35866,7 @@ static const insn_template i386_optab[] =
       0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
          0, 0, 0, 0, 0, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
          0, 0, 0, 0, 0, 0 } } } },
@@ -35886,7 +35886,7 @@ static const insn_template i386_optab[] =
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
          0, 0, 0, 0, 0, 0 } },
-      { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
+      { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
          0, 0, 0, 0, 0, 0 } } } },
   { MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,