GCN: '--param=gcn-preferred-vectorization-factor=[default,32,64]'

..., and specify '--param=gcn-preferred-vectorization-factor=64' for
'gcc.target/gcn/[...]' test cases with 'scan-assembler' directives that
are specific to 64-lane vectors.  This resolves regressions introduced
in commit 6dedafe166cc02ae87b6a0699ad61ce3ffc46803
"amdgcn: Prefer V32 on RDNA devices".

	gcc/
	* config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor):
	New.
	* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it.
	* doc/invoke.texi (Optimize Options): Document it.
	gcc/testsuite/
	* gcc.target/gcn/cond_fmaxnm_1.c: Specify
	'--param=gcn-preferred-vectorization-factor=64'.
	* gcc.target/gcn/cond_fmaxnm_2.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_3.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_4.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_5.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_6.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_7.c: Likewise.
	* gcc.target/gcn/cond_fmaxnm_8.c: Likewise.
	* gcc.target/gcn/cond_fminnm_1.c: Likewise.
	* gcc.target/gcn/cond_fminnm_2.c: Likewise.
	* gcc.target/gcn/cond_fminnm_3.c: Likewise.
	* gcc.target/gcn/cond_fminnm_4.c: Likewise.
	* gcc.target/gcn/cond_fminnm_5.c: Likewise.
	* gcc.target/gcn/cond_fminnm_6.c: Likewise.
	* gcc.target/gcn/cond_fminnm_7.c: Likewise.
	* gcc.target/gcn/cond_fminnm_8.c: Likewise.
	* gcc.target/gcn/cond_shift_3.c: Likewise.
	* gcc.target/gcn/cond_shift_4.c: Likewise.
	* gcc.target/gcn/cond_shift_8.c: Likewise.
	* gcc.target/gcn/cond_shift_9.c: Likewise.
	* gcc.target/gcn/cond_smax_1.c: Likewise.
	* gcc.target/gcn/cond_smin_1.c: Likewise.
	* gcc.target/gcn/cond_umax_1.c: Likewise.
	* gcc.target/gcn/cond_umin_1.c: Likewise.
	* gcc.target/gcn/simd-math-1.c: Likewise.
	* gcc.target/gcn/simd-math-5-char.c: Likewise.
	* gcc.target/gcn/simd-math-5-long.c: Likewise.
	* gcc.target/gcn/simd-math-5-short.c: Likewise.
	* gcc.target/gcn/simd-math-5.c: Likewise.
	* gcc.target/gcn/smax_1.c: Likewise.
	* gcc.target/gcn/smin_1.c: Likewise.
	* gcc.target/gcn/umax_1.c: Likewise.
	* gcc.target/gcn/umin_1.c: Likewise.

diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 700e554855e5f2a4ab240c48cb06bf6e4a852f01..9f91d4f9ebd10850da13104abcf530d2426dfd85 100644 (file)
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -5231,6 +5231,14 @@ gcn_vector_mode_supported_p (machine_mode mode)
 static machine_mode
 gcn_vectorize_preferred_simd_mode (scalar_mode mode)
 {
+  bool v32;
+  if (gcn_preferred_vectorization_factor == 32)
+    v32 = true;
+  else if (gcn_preferred_vectorization_factor == 64)
+    v32 = false;
+  else if (gcn_preferred_vectorization_factor != -1)
+    gcc_unreachable ();
+  else if (TARGET_RDNA2_PLUS)
   /* RDNA devices have 32-lane vectors with limited support for 64-bit vectors
      (in particular, permute operations are only available for cases that don't
      span the 32-lane boundary).
@@ -5238,7 +5246,11 @@ gcn_vectorize_preferred_simd_mode (scalar_mode mode)
      From the RDNA3 manual: "Hardware may choose to skip either half if the
      EXEC mask for that half is all zeros...". This means that preferring
      32-lanes is a good stop-gap until we have proper wave32 support.  */
-  if (TARGET_RDNA2_PLUS)
+    v32 = true;
+  else
+    v32 = false;
+
+  if (v32)
     switch (mode)
       {
       case E_QImode:

diff --git a/gcc/config/gcn/gcn.opt b/gcc/config/gcn/gcn.opt
index 1067b45f2947b8cec2b1d6c669f222c2b63a9f78..42bb5f75a426f80917fbc0f3b0c5bd61ef6e8abf 100644 (file)
--- a/gcc/config/gcn/gcn.opt
+++ b/gcc/config/gcn/gcn.opt
@@ -116,3 +116,19 @@ Compile for devices requiring XNACK enabled. Default \"any\" if USM is supported
 msram-ecc=
 Target RejectNegative Joined ToLower Enum(hsaco_attr_type) Var(flag_sram_ecc) Init(HSACO_ATTR_ANY)
 Compile for devices with the SRAM ECC feature enabled, or not. Default \"any\".
+
+-param=gcn-preferred-vectorization-factor=
+Target Joined Enum(gcn_preferred_vectorization_factor) Var(gcn_preferred_vectorization_factor) Init(-1) Param
+--param=gcn-preferred-vectorization-factor=[default,32,64]     Preferred vectorization factor.
+
+Enum
+Name(gcn_preferred_vectorization_factor) Type(int)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(default) Value(-1)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(32) Value(32)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(64) Value(64)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f5f5d83f8179b40203d49be9169af0bf2bfeec18..0b1230b7bc3c953ba8e688066d39f78bea8c4eea 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17017,6 +17017,14 @@ loop.  The default value is four.
 
 @end table
 
+The following choices of @var{name} are available on GCN targets:
+
+@table @gcctabopt
+@item gcn-preferred-vectorization-factor
+Preferred vectorization factor: @samp{default}, @samp{32}, @samp{64}.
+
+@end table
+
 The following choices of @var{name} are available on i386 and x86_64 targets:
 
 @table @gcctabopt

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
index 17c49bdc5189bfabcf87829d814e762f2b436492..29e77064bc506fc143019a2bcbb4bc67a4502c3a 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
index 406df48962a3f987b00ccb89b600e744a89ab416..f781ca2c0133f2e231172a1a5b917f8e25772852 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 45b8b7883ba5d6d9394ea539b2d30118fd56fe4b..5da33ac27267dbf573641d6559c7b115943e70bf 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 416aea89e6e2aee07ac9bfe008bf3260ef2c3270..263db35dd499e62f44e06ba5097ef422b8e7d430 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
index a4d7ab991de90e13632d738f4235b26cfa224436..6bfc2b9627f27e490c89981abd2aefda71e78053 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include "cond_fmaxnm_1.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
index 6c64a01bcbb963f87cc8f51b1ec935f49169982e..8ea52725cbee5455d0e2ef37b4d9f1d1ca941d07 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include "cond_fmaxnm_2.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
index bdb3f2f99ef51b33eff553d3f1137d842d54b5e6..97f8cf57ee32a6f8e428cb5fe2a6de101f8efb5b 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include "cond_fmaxnm_3.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
index c11633b5236c9332e31eea09fd53e26e1a26187b..9de89790a12378ee30b00b92d3f37e50825b39ba 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include "cond_fmaxnm_4.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
index bb4568875685d6ed39ca7d60be4c5268dd0f2088..7068e8c4f540c331f83350281f5a24a06b6709f8 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_1.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
index 502f8987494b120e8c6f86914a1102ee63c42f23..d8ee9446e3805a92bc91f715a52e0b2660ff7e9c 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_2.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index 2ea1eb2ec2ccba00bd43b7b8e9866e6c69608f8f..59bbc5610ced2f08c6f9ab1e4d1b71ed14a8d845 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_3.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index 3673ecafc2d136f129eddca54b1d7d17826731c6..07e6aae891977e02b42965e67f1300c6e7d4a3b1 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_4.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
index ac98941a3735bbf5326cd2c0524145ca1c53d804..84ab917043da3314bf01849cb4324bbcfd31eb59 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_1.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
index 7f4dba0d314bde04ed12b8919bc5c5457855c53b..a1525d91b33227e66069d36374c3f53225e2aa90 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_2.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
index 5faf0c5cc59ea970870c28c8704afa4b9dfbbd5a..bb5e0f24d5bb01c33bb6b232cb2d5a70e8505cf2 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_3.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
index 89d93ac596ab79a29e1df17859a0f90f17275f22..c090377c0e1800a01365ccf4a5f4ffa9832cbc15 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_4.c"

diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
index 983386c146461193d350c9cb06f35e9511912c90..1181384a4957520f63139cdbd81c3c477bb32aa2 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
index c610363d9df2b5e7a54800724a9674456c45a116..ea2110d0a6fe2cc98511eab52e04eba458e12790 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
index 0749e2e5e5378747ff89ae6b61ef87127b811995..9942a2e167cef76f9e9f91d00e0fefef987621ca 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
index 61aba27504e65b364d1bb12c2914d02e68b7937f..663192f97e78de36632ef49e150594ed5c5e6d92 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
index 342b5e827d2ed9f53424690b19eb7c0cc9cb2d4a..212091a15df76a769a033e982b83653c5febdb15 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
index ad8b583448b07dd10e9c3fc85a6f7a82a4a8e5bb..714aab2f7f77e51b5ef902afcba54f8c6f43c50c 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
index 389228f9e4afac616475706b133c0fde6a7a4de7..9018b0068176c51e19018c8a420ada7422de91f0 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
index 65759d695ad8bfd79601bc6583d272461d75dd5a..64d0a5eb3504a9d752831c2b9e1befafde685e20 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-1.c b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
index 6868ccb2c543c64e30a0b2cd91bbd382c9e1f56b..abd6a932a0192c80106c852d402b485586df15f3 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/simd-math-1.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
@@ -2,7 +2,8 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -fno-math-errno -mstack-size=3000000 -fdump-tree-vect" } */
-
+/* The 'scan-tree-dump' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #undef PRINT_RESULT
 #define VERBOSE 0

diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
index 2321c8390c6a1dd4acb38c77f9f18bc73a15be5f..e3521ce7ca3190d2b8188144344400ecf905497a 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
 #define TYPE char
 #include "simd-math-5.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
index 37b6cef691ed4350e45b164e5dc52c0d171ce634..96a9fd3e734e007c0b044c88608e26d1a4f829a8 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
 #define TYPE long
 #include "simd-math-5.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
index 84cdc9b5fdd64fa72703cf108b5b9cc696718bc2..c0bff40380a39c169c3c02636ee1d9800f05d56d 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
 #define TYPE short
 #include "simd-math-5.c"
 

diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5.c b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
index bc181b45e1b1bf16b8e857b7f0c01ed0c1077680..b5c5dc9f288e5b3caa6af0864f10d7d91b96151d 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
@@ -1,6 +1,9 @@
 /* Test that the auto-vectorizer uses the libgcc vectorized division and
    modulus functions.  */
 
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
 /* Setting it this way ensures the run tests use the same flag as the
    compile tests.  */
 #pragma GCC optimize("O2")

diff --git a/gcc/testsuite/gcc.target/gcn/smax_1.c b/gcc/testsuite/gcc.target/gcn/smax_1.c
index 46c21f73132955cc504e67a1575b392d55f1b6c3..eec050caf7119edb7025cde5dc18bb67fd6eeb9b 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smax_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/smin_1.c b/gcc/testsuite/gcc.target/gcn/smin_1.c
index 8d6edfaa3d1484423647f446b43aad80f27c10af..8aa8cbb9db88d5bddba2a01b835ca3c7d78a9a0e 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smin_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/umax_1.c b/gcc/testsuite/gcc.target/gcn/umax_1.c
index dc4b9842d9a8b3c2271c2da6e9e8b88b1365c16f..934bf9a4a7cbf146f5c3789ffb94c99bed412fba 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umax_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>
 

diff --git a/gcc/testsuite/gcc.target/gcn/umin_1.c b/gcc/testsuite/gcc.target/gcn/umin_1.c
index d07f7ec083b8a674b620cdba4b6bbcdf58eeee07..44343bd44cf961f96631e3b77190154d8aa0bacc 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umin_1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+   { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
 
 #include <stdint.h>