]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable
authorTaniya Das <quic_tdas@quicinc.com>
Wed, 12 Jun 2024 11:08:25 +0000 (16:38 +0530)
committerBjorn Andersson <andersson@kernel.org>
Sun, 23 Jun 2024 22:14:05 +0000 (17:14 -0500)
The RCG's clk src has to be parked at XO while disabling as per the
HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.
Also gpu_cc_cb_clk is recommended to be kept always ON, hence use
clk_branch2_aon_ops to keep the clock always ON.

Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/gpucc-sa8775p.c

index 72920f537f77eec3fa3bc110c75e836a1f023865..6abcdf357c341f45f211b179041d97d7f596a20b 100644 (file)
@@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = {
                .name = "gpu_cc_ff_clk_src",
                .parent_data = gpu_cc_parent_data_0,
                .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_shared_ops,
        },
 };
 
@@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
                .parent_data = gpu_cc_parent_data_1,
                .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
                .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_shared_ops,
        },
 };
 
@@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
                .name = "gpu_cc_hub_clk_src",
                .parent_data = gpu_cc_parent_data_2,
                .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_shared_ops,
        },
 };
 
@@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_cb_clk",
-                       .ops = &clk_branch2_ops,
+                       .ops = &clk_branch2_aon_ops,
                },
        },
 };