+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64 files.
+ * Makefile.in: Regenerate.
+ * archures.c (bfd_aarch64_arch): New declaration.
+ (bfd_archures_list): Use bfd_archures_list.
+ * bfd-in.h (bfd_elf64_aarch64_init_maps): New declaration.
+ (bfd_aarch64_process_before_allocation): New declaration.
+ (bfd_elf64_aarch64_process_before_allocation): New declaration.
+ (bfd_elf64_aarch64_set_options): New declaration.
+ (bfd_elf64_aarch64_add_glue_sections_to_bfd): New declaration.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_MAP): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_TAG): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_ANY): New definition.
+ (bfd_is_aarch64_special_symbol_name): New declaration.
+ (bfd_aarch64_merge_machines): New declaration.
+ (bfd_aarch64_update_notes): New declaration.
+ (int bfd_aarch64_get_mach_from_notes): New declaration.
+ (elf64_aarch64_setup_section_lists): New declaration.
+ (elf64_aarch64_next_input_section): New declaration.
+ (elf64_aarch64_size_stubs): New declaration.
+ (elf64_aarch64_build_stubs): New declaration.
+ * config.bfd: Add AArch64.
+ * configure.in: Add AArch64.
+ * configure: Regenerate.
+ * cpu-aarch64.c: New file.
+ * elf-bfd.h: Add AArch64.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+ * elf64-aarch64.c: New file.
+ * reloc.c: Add AArch64 relocations.
+ * targets.c: Add AArch64.
+ * po/SRC-POTFILES.in: Regenerate.
+
2012-08-14 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
+ cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
+ cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
+ elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
+ elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
+ cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
+ cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
+ elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
+ elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cofflink.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/compress.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/corefile.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
.#define bfd_mach_tilepro 1
.#define bfd_mach_tilegx 1
.#define bfd_mach_tilegx32 2
+. bfd_arch_aarch64, {* AArch64 *}
+.#define bfd_mach_aarch64 0
. bfd_arch_last
. };
*/
.
*/
+extern const bfd_arch_info_type bfd_aarch64_arch;
extern const bfd_arch_info_type bfd_alpha_arch;
extern const bfd_arch_info_type bfd_arc_arch;
extern const bfd_arch_info_type bfd_arm_arch;
#ifdef SELECT_ARCHITECTURES
SELECT_ARCHITECTURES,
#else
+ &bfd_aarch64_arch,
&bfd_alpha_arch,
&bfd_arc_arch,
&bfd_arm_arch,
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
+extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+void bfd_elf64_aarch64_set_options
+ (bfd *, struct bfd_link_info *, int, int, int);
+
+/* ELF AArch64 mapping symbol support. */
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
+extern bfd_boolean bfd_is_aarch64_special_symbol_name
+ (const char * name, int type);
+
+/* AArch64 stub generation support. Called from the linker. */
+extern int elf64_aarch64_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+extern void elf64_aarch64_next_input_section
+ (struct bfd_link_info *, struct bfd_section *);
+extern bfd_boolean elf64_aarch64_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ struct bfd_section * (*) (const char *, struct bfd_section *),
+ void (*) (void));
+extern bfd_boolean elf64_aarch64_build_stubs
+ (struct bfd_link_info *);
+
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
+extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+void bfd_elf64_aarch64_set_options
+ (bfd *, struct bfd_link_info *, int, int, int);
+
+/* ELF AArch64 mapping symbol support. */
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
+extern bfd_boolean bfd_is_aarch64_special_symbol_name
+ (const char * name, int type);
+
+/* AArch64 stub generation support. Called from the linker. */
+extern int elf64_aarch64_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+extern void elf64_aarch64_next_input_section
+ (struct bfd_link_info *, struct bfd_section *);
+extern bfd_boolean elf64_aarch64_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ struct bfd_section * (*) (const char *, struct bfd_section *),
+ void (*) (void));
+extern bfd_boolean elf64_aarch64_build_stubs
+ (struct bfd_link_info *);
+
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
#define bfd_mach_tilepro 1
#define bfd_mach_tilegx 1
#define bfd_mach_tilegx32 2
+ bfd_arch_aarch64, /* AArch64 */
+#define bfd_mach_aarch64 0
bfd_arch_last
};
the dynamic object into the runtime process image. */
BFD_RELOC_MICROBLAZE_COPY,
+/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_ADD_LO12,
+
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 21 bit PC relative value.Used in
+conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address. */
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address, but with no overflow
+checking. */
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+
+/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL,
+
+/* AArch64 19 bit pc-relative conditional branch and compare & branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_BRANCH19,
+
+/* AArch64 26 bit pc-relative unconditional branch and link.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_CALL26,
+
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
+
+/* AArch64 26 bit pc-relative unconditional branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_JUMP26,
+
+/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+offset. The lowest two bits must be zero and are not stored in the
+instruction, giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_LD_LO19_PCREL,
+
+/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. */
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
+
+/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST_LO12,
+
+/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST8_LO12,
+
+/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST16_LO12,
+
+/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST32_LO12,
+
+/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST64_LO12,
+
+/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST128_LO12,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G0,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G1,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G2,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+
+/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+of a signed or unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G3,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLSDESC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_CALL,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LDR,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
+
+/* Unsigned 12 bit byte offset to global offset table entry for a symbols
+tls_index structure. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+
+/* Get to the page base of the global offset table entry for a symbols
+tls_index structure as part of an adrp instruction using a 21 bit PC
+relative value. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPMOD64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPREL64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_TPREL64,
+
+/* AArch64 14 bit pc-relative test bit and branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 16 bit signed byte offset. */
+ BFD_RELOC_AARCH64_TSTBR14,
+
/* Tilera TILEPro Relocations. */
BFD_RELOC_TILEPRO_COPY,
BFD_RELOC_TILEPRO_GLOB_DAT,
targ_cpu=`echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
case "${targ_cpu}" in
+aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";;
alpha*) targ_archs=bfd_alpha_arch ;;
am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
arm*) targ_archs=bfd_arm_arch ;;
# START OF targmatch.h
#ifdef BFD64
+ aarch64-*-elf)
+ targ_defvec=bfd_elf64_littleaarch64_vec
+ targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
+ want64=true
+ ;;
+ aarch64_be-*-elf)
+ targ_defvec=bfd_elf64_bigaarch64_vec
+ targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
+ want64=true
+ ;;
+ aarch64-*-linux*)
+ targ_defvec=bfd_elf64_littleaarch64_vec
+ targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
+ want64=true
+ ;;
+ aarch64_be-*-linux*)
+ targ_defvec=bfd_elf64_bigaarch64_vec
+ targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
+ want64=true
+ ;;
alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
targ_defvec=bfd_elf64_alpha_freebsd_vec
targ_selvecs="bfd_elf64_alpha_vec ecoffalpha_little_vec"
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
+ bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
+ bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
+ bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
+ bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(bfd_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/bfd.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
$(top_srcdir)/../config/stdint.m4 $(top_srcdir)/../libtool.m4 \
$(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
$(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
- $(top_srcdir)/bfd.m4 $(top_srcdir)/warning.m4 \
$(top_srcdir)/acinclude.m4 $(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
one line. */
enum elf_target_id
{
- ALPHA_ELF_DATA = 1,
+ AARCH64_ELF_DATA = 1,
+ ALPHA_ELF_DATA,
ARM_ELF_DATA,
AVR_ELF_DATA,
BFIN_ELF_DATA,
elf64_aarch64_final_link_relocate ()
- Fixup the R_AARCH64_TLSGD_{ADR_PREL21, ADD_LO12_NC} relocations. */
+ Fixup the R_AARCH64_TLSGD_{ADR_PREL21, ADD_LO12_NC} relocations.
+
+ */
#include "sysdep.h"
#include "bfd.h"
#define PLT_SMALL_ENTRY_SIZE (16)
#define PLT_TLSDESC_ENTRY_SIZE (32)
-/* Take the PAGE component of an address or offset. */
+/* Take the PAGE component of an address or offset. */
#define PG(x) ((x) & ~ 0xfff)
#define PG_OFFSET(x) ((x) & 0xfff)
these PLT entries. Note that the dynamic linker gets &PLTGOT[2]
in x16 and needs to work out PLTGOT[1] by using an address of
[x16,#-8]. */
-static const bfd_byte elf64_aarch64_small_plt0_entry[PLT_ENTRY_SIZE] =
-{
+static const bfd_byte elf64_aarch64_small_plt0_entry[PLT_ENTRY_SIZE] = {
0xf0, 0x7b, 0xbf, 0xa9, /* stp x16, x30, [sp, #-16]! */
0x10, 0x00, 0x00, 0x90, /* adrp x16, (GOT+16) */
0x11, 0x0A, 0x40, 0xf9, /* ldr x17, [x16, #PLT_GOT+0x10] */
/* Per function entry in a procedure linkage table looks like this
if the distance between the PLTGOT and the PLT is < 4GB use
these PLT entries. */
-static const bfd_byte elf64_aarch64_small_plt_entry[PLT_SMALL_ENTRY_SIZE] =
-{
+static const bfd_byte elf64_aarch64_small_plt_entry[PLT_SMALL_ENTRY_SIZE] = {
0x10, 0x00, 0x00, 0x90, /* adrp x16, PLTGOT + n * 8 */
0x11, 0x02, 0x40, 0xf9, /* ldr x17, [x16, PLTGOT + n * 8] */
0x10, 0x02, 0x00, 0x91, /* add x16, x16, :lo12:PLTGOT + n * 8 */
};
static const bfd_byte
-elf64_aarch64_tlsdesc_small_plt_entry[PLT_TLSDESC_ENTRY_SIZE] =
-{
+ elf64_aarch64_tlsdesc_small_plt_entry[PLT_TLSDESC_ENTRY_SIZE] = {
0xe2, 0x0f, 0xbf, 0xa9, /* stp x2, x3, [sp, #-16]! */
0x02, 0x00, 0x00, 0x90, /* adrp x2, 0 */
0x03, 0x00, 0x00, 0x90, /* adrp x3, 0 */
0, /* dst_mask */
FALSE); /* pcrel_offset */
-static reloc_howto_type elf64_aarch64_howto_dynrelocs[] =
-{
+static reloc_howto_type elf64_aarch64_howto_dynrelocs[] = {
+
HOWTO (R_AARCH64_COPY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
R_AARCH64_PREL64 as an index into this, and find the R_AARCH64_PREL64 HOWTO
in that slot. */
-static reloc_howto_type elf64_aarch64_howto_table[] =
-{
- /* Basic data relocations. */
+static reloc_howto_type elf64_aarch64_howto_table[] = {
+ /* Basic data relocations. */
HOWTO (R_AARCH64_NULL, /* type */
0, /* rightshift */
TRUE), /* pcrel_offset */
/* Group relocations to create a 16, 32, 48 or 64 bit
- unsigned data or abs address inline. */
+ unsigned data or abs address inline. */
/* MOVZ: ((S+A) >> 0) & 0xffff */
HOWTO (R_AARCH64_MOVW_UABS_G0, /* type */
/* Group relocations to create high part of a 16, 32, 48 or 64 bit
signed data or abs address inline. Will change instruction
- to MOVN or MOVZ depending on sign of calculated value. */
+ to MOVN or MOVZ depending on sign of calculated value. */
/* MOV[ZN]: ((S+A) >> 0) & 0xffff */
HOWTO (R_AARCH64_MOVW_SABS_G0, /* type */
FALSE), /* pcrel_offset */
/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
- addresses: PG(x) is (x & ~0xfff). */
+ addresses: PG(x) is (x & ~0xfff). */
/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
HOWTO (R_AARCH64_LD_PREL_LO19, /* type */
0xfff, /* dst_mask */
FALSE), /* pcrel_offset */
- /* Relocations for control-flow instructions. */
+ /* Relocations for control-flow instructions. */
/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff */
HOWTO (R_AARCH64_TSTBR14, /* type */
FALSE) /* pcrel_offset */
};
-static reloc_howto_type elf64_aarch64_tls_howto_table[] =
-{
+static reloc_howto_type elf64_aarch64_tls_howto_table[] = {
EMPTY_HOWTO (512),
/* Get to the page for the GOT entry for the symbol
FALSE), /* pcrel_offset */
};
-static reloc_howto_type elf64_aarch64_tlsdesc_howto_table[] =
-{
+static reloc_howto_type elf64_aarch64_tlsdesc_howto_table[] = {
HOWTO (R_AARCH64_TLSDESC_LD64_PREL19, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
/* All entries in this list must also be present in
elf64_aarch64_howto_table. */
-static const struct elf64_aarch64_reloc_map elf64_aarch64_reloc_map[] =
-{
+static const struct elf64_aarch64_reloc_map elf64_aarch64_reloc_map[] = {
{BFD_RELOC_NONE, R_AARCH64_NONE},
/* Basic data relocations. */
{BFD_RELOC_AARCH64_LDST64_LO12, R_AARCH64_LDST64_ABS_LO12_NC},
{BFD_RELOC_AARCH64_LDST128_LO12, R_AARCH64_LDST128_ABS_LO12_NC},
- /* Relocations for control-flow instructions. */
+ /* Relocations for control-flow instructions. */
{BFD_RELOC_AARCH64_TSTBR14, R_AARCH64_TSTBR14},
{BFD_RELOC_AARCH64_BRANCH19, R_AARCH64_CONDBR19},
{BFD_RELOC_AARCH64_JUMP26, R_AARCH64_JUMP26},
{BFD_RELOC_AARCH64_ADR_GOT_PAGE, R_AARCH64_ADR_GOT_PAGE},
{BFD_RELOC_AARCH64_LD64_GOT_LO12_NC, R_AARCH64_LD64_GOT_LO12_NC},
- /* Relocations for TLS. */
+ /* Relocations for TLS. */
{BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21, R_AARCH64_TLSGD_ADR_PAGE21},
{BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, R_AARCH64_TLSGD_ADD_LO12_NC},
{BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
&& offset >= AARCH64_MAX_BWD_BRANCH_OFFSET);
}
-static const uint32_t aarch64_adrp_branch_stub [] =
-{
+static const uint32_t aarch64_adrp_branch_stub [] = {
0x90000010, /* adrp ip0, X */
/* R_AARCH64_ADR_HI21_PCREL(X) */
0x91000210, /* add ip0, ip0, :lo12:X */
0xd61f0200, /* br ip0 */
};
-static const uint32_t aarch64_long_branch_stub[] =
-{
+static const uint32_t aarch64_long_branch_stub[] = {
0x58000090, /* ldr ip0, 1f */
0x10000011, /* adr ip1, #0 */
0x8b110210, /* add ip0, ip0, ip1 */
/* Base hash table entry structure. */
struct bfd_hash_entry root;
+
/* The stub section. */
asection *stub_sec;
if (stub_group_size == 1)
{
/* Default values. */
- /* Aarch64 branch range is +-128MB. The value used is 1MB less. */
+ /* Aarch64 branch range is +-128MB. The value used is 1MB less. */
stub_group_size = 127 * 1024 * 1024;
}
sym_sec = hdr->bfd_section;
if (!sym_sec)
/* This is an undefined symbol. It can never
- be resolved. */
+ be resolved. */
continue;
if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
}
-/* Encode the 14-bit offset of test & branch. */
+/* Encode the 14-bit offset of test & branch. */
static inline uint32_t
reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
{
return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5);
}
-/* Reencode the imm field of move wide. */
+/* Reencode the imm field of move wide. */
static inline uint32_t
reencode_movw_imm (uint32_t insn, uint32_t imm)
{
return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
}
-/* Reencode the imm field of add immediate. */
+/* Reencode the imm field of add immediate. */
static inline uint32_t
reencode_add_imm (uint32_t insn, uint32_t imm)
{
return opcode | (1 << 30);
}
-/* Reencode mov[zn] to movn. */
+/* Reencode mov[zn] to movn. */
static inline uint32_t
reencode_movzn_to_movn (uint32_t opcode)
{
return bfd_reloc_overflow;
/* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order
12 bits of the page offset following R_AARCH64_ADR_PREL_PG_HI21
- which computes the (pc-relative) page base. */
+ which computes the (pc-relative) page base. */
contents = reencode_ldst_pos_imm (contents, addend);
break;
/* Group relocations to create high bits of a 16, 32, 48 or 64
bit signed data or abs address inline. Will change
instruction to MOVN or MOVZ depending on sign of calculated
- value. */
+ value. */
case R_AARCH64_TLSLE_MOVW_TPREL_G2:
case R_AARCH64_TLSLE_MOVW_TPREL_G1:
case R_AARCH64_MOVW_SABS_G0:
case R_AARCH64_MOVW_SABS_G1:
case R_AARCH64_MOVW_SABS_G2:
- /* NOTE: We can only come here with movz or movn. */
+ /* NOTE: We can only come here with movz or movn. */
if (addend < 0)
{
/* Force use of MOVN. */
/* fall through */
/* Group relocations to create a 16, 32, 48 or 64 bit unsigned
- data or abs address inline. */
+ data or abs address inline. */
case R_AARCH64_MOVW_UABS_G0:
case R_AARCH64_MOVW_UABS_G0_NC:
}
/* Return the base VMA address which should be subtracted from real addresses
- when resolving R_AARCH64_TLS_DTPREL64 relocation. */
+ when resolving R_AARCH64_TLS_DTPREL64 relocation. */
static bfd_vma
dtpoff_base (struct bfd_link_info *info)
+ input_section->output_offset + rel->r_offset;
/* Get addend, accumulating the addend for consecutive relocs
- which refer to the same offset. */
+ which refer to the same offset. */
signed_addend = saved_addend ? *saved_addend : 0;
signed_addend += rel->r_addend;
{
/* Sanity to check that we have previously allocated
sufficient space in the relocation section for the
- number of relocations we actually want to emit. */
+ number of relocations we actually want to emit. */
abort ();
}
/* A call to an undefined weak symbol is converted to a jump to
the next instruction unless a PLT entry will be created.
The jump to the next instruction is optimized as a NOP.
- Do the same for local undefined symbols. */
+ Do the same for local undefined symbols. */
if (weak_undef_p && ! via_plt_p)
{
bfd_putl32 (INSN_NOP, hit_data);
}
else
{
- /* Track dynamic relocs needed for local syms too.
- We really need local syms available to do this
- easily. Oh well. */
+ /* Track dynamic relocs needed for local syms too.
+ We really need local syms available to do this
+ easily. Oh well. */
asection *s;
void **vpp;
/* We use this so we can override certain functions
(though currently we don't). */
-const struct elf_size_info elf64_aarch64_size_info =
-{
+const struct elf_size_info elf64_aarch64_size_info = {
sizeof (Elf64_External_Ehdr),
sizeof (Elf64_External_Phdr),
sizeof (Elf64_External_Shdr),
sizeof (Elf64_External_Sym),
sizeof (Elf64_External_Dyn),
sizeof (Elf_External_Note),
- 4, /* Hash table entry size. */
- 1, /* Internal relocs per external relocs. */
- 64, /* Arch size. */
- 3, /* Log_file_align. */
+ 4, /* hash-table entry size. */
+ 1, /* internal relocs per external relocs. */
+ 64, /* arch_size. */
+ 3, /* log_file_align. */
ELFCLASS64, EV_CURRENT,
bfd_elf64_write_out_phdrs,
bfd_elf64_write_shdrs_and_ehdr,
"BFD_RELOC_MICROBLAZE_64_GOTOFF",
"BFD_RELOC_MICROBLAZE_32_GOTOFF",
"BFD_RELOC_MICROBLAZE_COPY",
+ "BFD_RELOC_AARCH64_ADD_LO12",
+ "BFD_RELOC_AARCH64_ADR_GOT_PAGE",
+ "BFD_RELOC_AARCH64_ADR_HI21_PCREL",
+ "BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL",
+ "BFD_RELOC_AARCH64_ADR_LO21_PCREL",
+ "BFD_RELOC_AARCH64_BRANCH19",
+ "BFD_RELOC_AARCH64_CALL26",
+ "BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP",
+ "BFD_RELOC_AARCH64_JUMP26",
+ "BFD_RELOC_AARCH64_LD_LO19_PCREL",
+ "BFD_RELOC_AARCH64_LD64_GOT_LO12_NC",
+ "BFD_RELOC_AARCH64_LDST_LO12",
+ "BFD_RELOC_AARCH64_LDST8_LO12",
+ "BFD_RELOC_AARCH64_LDST16_LO12",
+ "BFD_RELOC_AARCH64_LDST32_LO12",
+ "BFD_RELOC_AARCH64_LDST64_LO12",
+ "BFD_RELOC_AARCH64_LDST128_LO12",
+ "BFD_RELOC_AARCH64_MOVW_G0",
+ "BFD_RELOC_AARCH64_MOVW_G0_S",
+ "BFD_RELOC_AARCH64_MOVW_G0_NC",
+ "BFD_RELOC_AARCH64_MOVW_G1",
+ "BFD_RELOC_AARCH64_MOVW_G1_NC",
+ "BFD_RELOC_AARCH64_MOVW_G1_S",
+ "BFD_RELOC_AARCH64_MOVW_G2",
+ "BFD_RELOC_AARCH64_MOVW_G2_NC",
+ "BFD_RELOC_AARCH64_MOVW_G2_S",
+ "BFD_RELOC_AARCH64_MOVW_G3",
+ "BFD_RELOC_AARCH64_TLSDESC",
+ "BFD_RELOC_AARCH64_TLSDESC_ADD",
+ "BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE",
+ "BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21",
+ "BFD_RELOC_AARCH64_TLSDESC_CALL",
+ "BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19",
+ "BFD_RELOC_AARCH64_TLSDESC_LDR",
+ "BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_OFF_G1",
+ "BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21",
+ "BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21",
+ "BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19",
+ "BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC",
+ "BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2",
+ "BFD_RELOC_AARCH64_TLS_DTPMOD64",
+ "BFD_RELOC_AARCH64_TLS_DTPREL64",
+ "BFD_RELOC_AARCH64_TLS_TPREL64",
+ "BFD_RELOC_AARCH64_TSTBR14",
"BFD_RELOC_TILEPRO_COPY",
"BFD_RELOC_TILEPRO_GLOB_DAT",
"BFD_RELOC_TILEPRO_JMP_SLOT",
This is used to tell the dynamic linker to copy the value out of
the dynamic object into the runtime process image.
+ENUM
+ BFD_RELOC_AARCH64_ADD_LO12
+ENUMDOC
+ AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+ Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE
+ENUMDOC
+ Get to the page base of the global offset table entry for a symbol as
+ part of an ADRP instruction using a 21 bit PC relative value.Used in
+ conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
+ENUM
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL
+ENUMDOC
+ AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+ offset, giving a 4KB aligned page base address.
+ENUM
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
+ENUMDOC
+ AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+ offset, giving a 4KB aligned page base address, but with no overflow
+ checking.
+ENUM
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL
+ENUMDOC
+ AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
+ENUM
+ BFD_RELOC_AARCH64_BRANCH19
+ENUMDOC
+ AArch64 19 bit pc-relative conditional branch and compare & branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 21 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_CALL26
+ENUMDOC
+ AArch64 26 bit pc-relative unconditional branch and link.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 28 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
+ENUMDOC
+ AArch64 pseudo relocation code to be used internally by the AArch64
+ assembler and not (currently) written to any object files.
+ENUM
+ BFD_RELOC_AARCH64_JUMP26
+ENUMDOC
+ AArch64 26 bit pc-relative unconditional branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 28 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_LD_LO19_PCREL
+ENUMDOC
+ AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+ offset. The lowest two bits must be zero and are not stored in the
+ instruction, giving a 21 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
+ENUMDOC
+ Unsigned 12 bit byte offset for 64 bit load/store from the page of
+ the GOT entry for this symbol. Used in conjunction with
+ BFD_RELOC_AARCH64_ADR_GOTPAGE.
+ENUM
+ BFD_RELOC_AARCH64_LDST_LO12
+ENUMDOC
+ AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST8_LO12
+ENUMDOC
+ AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST16_LO12
+ENUMDOC
+ AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST32_LO12
+ENUMDOC
+ AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST64_LO12
+ENUMDOC
+ AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST128_LO12
+ENUMDOC
+ AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+ an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+ of an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+ of an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G3
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+ of a signed or unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADD
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_CALL
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LDR
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
+ENUMDOC
+ Unsigned 12 bit byte offset to global offset table entry for a symbols
+ tls_index structure. Used in conjunction with
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
+ENUM
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
+ENUMDOC
+ Get to the page base of the global offset table entry for a symbols
+ tls_index structure as part of an adrp instruction using a 21 bit PC
+ relative value. Used in conjunction with
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_DTPMOD64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_DTPREL64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_TPREL64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TSTBR14
+ENUMDOC
+ AArch64 14 bit pc-relative test bit and branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 16 bit signed byte offset.
+
ENUM
BFD_RELOC_TILEPRO_COPY
ENUMX
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
ENUMDOC
Tilera TILEPro Relocations.
-
ENUM
BFD_RELOC_TILEGX_HW0
ENUMX
BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
ENUMDOC
Tilera TILE-Gx Relocations.
-
ENUM
BFD_RELOC_EPIPHANY_SIMM8
ENUMDOC
extern const bfd_target bfd_elf64_alpha_vec;
extern const bfd_target bfd_elf64_big_generic_vec;
extern const bfd_target bfd_elf64_bigmips_vec;
+extern const bfd_target bfd_elf64_bigaarch64_vec;
extern const bfd_target bfd_elf64_hppa_linux_vec;
extern const bfd_target bfd_elf64_hppa_vec;
extern const bfd_target bfd_elf64_ia64_big_vec;
extern const bfd_target bfd_elf64_ia64_vms_vec;
extern const bfd_target bfd_elf64_little_generic_vec;
extern const bfd_target bfd_elf64_littlemips_vec;
+extern const bfd_target bfd_elf64_littleaarch64_vec;
extern const bfd_target bfd_elf64_mmix_vec;
extern const bfd_target bfd_elf64_powerpc_vec;
extern const bfd_target bfd_elf64_powerpcle_vec;
&bfd_elf64_alpha_vec,
&bfd_elf64_big_generic_vec,
&bfd_elf64_bigmips_vec,
+ &bfd_elf64_bigaarch64_vec,
&bfd_elf64_hppa_linux_vec,
&bfd_elf64_hppa_vec,
&bfd_elf64_ia64_big_vec,
&bfd_elf64_ia64_vms_vec,
&bfd_elf64_little_generic_vec,
&bfd_elf64_littlemips_vec,
+ &bfd_elf64_littleaarch64_vec,
&bfd_elf64_mmix_vec,
&bfd_elf64_powerpc_vec,
&bfd_elf64_powerpcle_vec,
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * readelf.c (guess_is_rela): Handle EM_AARCH64.
+ (get_machine_name): Likewise.
+ (get_aarch64_segment_type): New function.
+ (get_segment_type): Handle EM_AARCH64 by calling the new function.
+ (get_aarch64_section_type_name): New function.
+ (get_section_type_name): Handle EM_AARCH64 by calling the new function.
+ (is_32bit_abs_reloc): Handle EM_AARCH64.
+ (is_32bit_pcrel_reloc): Likewise.
+ (is_64bit_abs_reloc): Likewise.
+ (is_64bit_pcrel_reloc): Likewise.
+ (is_none_reloc): Likewise.
+
2012-08-09 Nick Clifton <nickc@redhat.com>
* po/vi.po: Updated Vietnamese translation.
responsibility among the other maintainers.
ALPHA Richard Henderson <rth@redhat.com>
+ AARCH64 Richard Earnshaw <rearnsha@arm.com>
ARM Nick Clifton <nickc@redhat.com>
ARM Richard Earnshaw <rearnsha@arm.com>
ARM Paul Brook <paul@codesourcery.com>
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/zlib.m4 \
- $(top_srcdir)/../bfd/warning.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/iconv.m4 \
#define RELOC_MACROS_GEN_FUNC
+#include "elf/aarch64.h"
#include "elf/alpha.h"
#include "elf/arc.h"
#include "elf/arm.h"
/* Targets that use RELA relocations. */
case EM_68K:
case EM_860:
+ case EM_AARCH64:
case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
case EM_ALTERA_NIOS2:
rtype = NULL;
break;
+ case EM_AARCH64:
+ rtype = elf_aarch64_reloc_type (type);
+ break;
+
case EM_M32R:
case EM_CYGNUS_M32R:
rtype = elf_m32r_reloc_type (type);
switch (e_machine)
{
case EM_NONE: return _("None");
+ case EM_AARCH64: return "AArch64";
case EM_M32: return "WE32100";
case EM_SPARC: return "Sparc";
case EM_SPU: return "SPU";
}
}
+static const char *
+get_aarch64_segment_type (unsigned long type)
+{
+ switch (type)
+ {
+ case PT_AARCH64_ARCHEXT:
+ return "AARCH64_ARCHEXT";
+ default:
+ break;
+ }
+
+ return NULL;
+}
+
static const char *
get_arm_segment_type (unsigned long type)
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ result = get_aarch64_segment_type (p_type);
+ break;
case EM_ARM:
result = get_arm_segment_type (p_type);
break;
return NULL;
}
+static const char *
+get_aarch64_section_type_name (unsigned int sh_type)
+{
+ switch (sh_type)
+ {
+ case SHT_AARCH64_ATTRIBUTES:
+ return "AARCH64_ATTRIBUTES";
+ default:
+ break;
+ }
+ return NULL;
+}
+
static const char *
get_arm_section_type_name (unsigned int sh_type)
{
case EM_K1OM:
result = get_x86_64_section_type_name (sh_type);
break;
+ case EM_AARCH64:
+ result = get_aarch64_section_type_name (sh_type);
+ break;
case EM_ARM:
result = get_arm_section_type_name (sh_type);
break;
return reloc_type == 1; /* R_860_32. */
case EM_960:
return reloc_type == 2; /* R_960_32. */
+ case EM_AARCH64:
+ return reloc_type == 258; /* R_AARCH64_ABS32 */
case EM_ALPHA:
return reloc_type == 1; /* R_ALPHA_REFLONG. */
case EM_ARC:
return reloc_type == 2; /* R_386_PC32. */
case EM_68K:
return reloc_type == 4; /* R_68K_PC32. */
+ case EM_AARCH64:
+ return reloc_type == 261; /* R_AARCH64_PREL32 */
case EM_ADAPTEVA_EPIPHANY:
return reloc_type == 6;
case EM_ALPHA:
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ return reloc_type == 257; /* R_AARCH64_ABS64. */
case EM_ALPHA:
return reloc_type == 2; /* R_ALPHA_REFQUAD. */
case EM_IA_64:
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ return reloc_type == 260; /* R_AARCH64_PREL64. */
case EM_ALPHA:
return reloc_type == 11; /* R_ALPHA_SREL64. */
case EM_IA_64:
case EM_XC16X:
case EM_C166: /* R_XC16X_NONE. */
return reloc_type == 0;
+ case EM_AARCH64:
+ return reloc_type == 0 || reloc_type == 256;
case EM_XTENSA_OLD:
case EM_XTENSA:
return (reloc_type == 0 /* R_XTENSA_NONE. */
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * objdump.exp: Add AArch64.
+
2012-07-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/14319
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected alpha arc arm cris
+lappend cpus_expected aarch64 alpha arc arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp ns32k pj powerpc pyramid
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * config/tc-aarch64.c: New file.
+ * config/tc-aarch64.h: New file.
+ * configure.tgt: Add AArch64.
+ * doc/Makefile.am: Add AArch64.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add AArch64.
+ * doc/as.texinfo: Add AArch64.
+ * doc/c-aarch64.texi: New file.
+ * po/POTFILES.in: Regenerate.
+ * NEWS: Mention the new support.
+
2012-07-20 James Murray <jsm@jsm-net.demon.co.uk>
* config/tc-m68hc11.c (build_indexed_byte): Replace use of binary
# CPU files in config.
TARGET_CPU_CFILES = \
+ config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
+ config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \
# CPU files in config.
TARGET_CPU_CFILES = \
+ config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
+ config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stabs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/subsegs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/symbols.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-aarch64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-alpha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $<
+tc-aarch64.o: config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.o -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
+
+tc-aarch64.obj: config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.obj -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
+
tc-alpha.o: config/tc-alpha.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-alpha.o -MD -MP -MF $(DEPDIR)/tc-alpha.Tpo -c -o tc-alpha.o `test -f 'config/tc-alpha.c' || echo '$(srcdir)/'`config/tc-alpha.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-alpha.Tpo $(DEPDIR)/tc-alpha.Po
Changes in 2.23:
+* Add support for 64-bit ARM architecture: AArch64
+
* Add support for S12X processor.
* Add support for the VLE extension to the PowerPC architecture.
# endian and arch.
# Note: This table is alpha-sorted, please try to keep it that way.
case ${cpu} in
+ aarch64) cpu_type=aarch64 endian=little ;;
+ aarch64_be) cpu_type=aarch64 endian=big ;;
alpha*) cpu_type=alpha ;;
am33_2.0) cpu_type=mn10300 endian=little ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
generic_target=${cpu_type}-$vendor-$os
# Note: This table is alpha-sorted, please try to keep it that way.
case ${generic_target} in
+ aarch64*-*-elf) fmt=elf;;
+ aarch64*-*-linux*) fmt=elf em=linux ;;
+
alpha-*-*vms*) fmt=evax ;;
alpha-*-osf*) fmt=ecoff ;;
alpha-*-linuxecoff*) fmt=ecoff ;;
esac
case ${cpu_type} in
- alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
+ aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
bfd_gas=yes
;;
esac
chmod u+w ./asconfig.texi
CPU_DOCS = \
+ c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(as_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+ $(top_srcdir)/../config/zlib.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
$(top_srcdir)/../config/plugins.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
- $(top_srcdir)/../bfd/acinclude.m4 \
- $(top_srcdir)/../config/zlib.m4 \
- $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/acinclude.m4 \
+ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
$(ACLOCAL_M4)
DATADIRNAME = @DATADIRNAME@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
-DLLTOOL = @DLLTOOL@
DSYMUTIL = @DSYMUTIL@
DUMPBIN = @DUMPBIN@
ECHO_C = @ECHO_C@
LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
-MANIFEST_TOOL = @MANIFEST_TOOL@
MKDIR_P = @MKDIR_P@
MKINSTALLDIRS = @MKINSTALLDIRS@
MSGFMT = @MSGFMT@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
abs_top_srcdir = @abs_top_srcdir@
-ac_ct_AR = @ac_ct_AR@
ac_ct_CC = @ac_ct_CC@
ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
am__include = @am__include@
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
CPU_DOCS = \
+ c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \
@c CPUs of interest
@c ================
+@set AARCH64
@set ALPHA
@set ARC
@set ARM
@c
@c Target dependent options are listed below. Keep the list sorted.
@c Add an empty line for separation.
+@ifset AARCH64
+
+@emph{Target AArch64 options:}
+ [@b{-EB}|@b{-EL}]
+@end ifset
@ifset ALPHA
@emph{Target Alpha options:}
@end table
@c man end
+@ifset AARCH64
+
+@ifclear man
+@xref{AArch64 Options}, for the options available when @value{AS} is configured
+for the 64-bit mode of the ARM Architecture (AArch64).
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for the
+64-bit mode of the ARM Architecture (AArch64).
+@c man end
+@c man begin INCLUDE
+@include c-aarch64.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@ifset ALPHA
@ifclear man
subject, see the hardware manufacturer's manual.
@menu
+@ifset AARCH64
+* AArch64-Dependent:: AArch64 Dependent Features
+@end ifset
@ifset ALPHA
* Alpha-Dependent:: Alpha Dependent Features
@end ifset
@c node and sectioning commands; hence the repetition of @chapter BLAH
@c in both conditional blocks.
+@ifset AARCH64
+@include c-aarch64.texi
+@end ifset
+
@ifset ALPHA
@include c-alpha.texi
@end ifset
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * gas/aarch64: New directory.
+ * gas/aarch64/aarch64.exp: New file.
+ * gas/aarch64/addsub.d: New file.
+ * gas/aarch64/addsub.s: New file.
+ * gas/aarch64/advsimd-across.d: New file.
+ * gas/aarch64/advsimd-across.s: New file.
+ * gas/aarch64/advsimd-misc.d: New file.
+ * gas/aarch64/advsimd-misc.s: New file.
+ * gas/aarch64/advsisd-copy.d: New file.
+ * gas/aarch64/advsisd-copy.s: New file.
+ * gas/aarch64/advsisd-misc.d: New file.
+ * gas/aarch64/advsisd-misc.s: New file.
+ * gas/aarch64/alias.d: New file.
+ * gas/aarch64/alias.s: New file.
+ * gas/aarch64/bitfield-alias.d: New file.
+ * gas/aarch64/bitfield-alias.s: New file.
+ * gas/aarch64/bitfield-bfm.d: New file.
+ * gas/aarch64/bitfield-bfm.s: New file.
+ * gas/aarch64/bitfield-dump: New file.
+ * gas/aarch64/bitfield-no-aliases.d: New file.
+ * gas/aarch64/crypto.d: New file.
+ * gas/aarch64/crypto.s: New file.
+ * gas/aarch64/diagnostic.d: New file.
+ * gas/aarch64/diagnostic.l: New file.
+ * gas/aarch64/diagnostic.s: New file.
+ * gas/aarch64/floatdp2.d: New file.
+ * gas/aarch64/floatdp2.s: New file.
+ * gas/aarch64/fp_cvt_int.d: New file.
+ * gas/aarch64/fp_cvt_int.s: New file.
+ * gas/aarch64/illegal-2.d: New file.
+ * gas/aarch64/illegal-2.l: New file.
+ * gas/aarch64/illegal-2.s: New file.
+ * gas/aarch64/illegal.d: New file.
+ * gas/aarch64/illegal.l: New file.
+ * gas/aarch64/illegal.s: New file.
+ * gas/aarch64/inst-directive.d: New file.
+ * gas/aarch64/inst-directive.s: New file.
+ * gas/aarch64/int-insns.d: New file.
+ * gas/aarch64/int-insns.s: New file.
+ * gas/aarch64/ldst-exclusive.d: New file.
+ * gas/aarch64/ldst-exclusive.s: New file.
+ * gas/aarch64/ldst-reg-imm-post-ind.d: New file.
+ * gas/aarch64/ldst-reg-imm-post-ind.s: New file.
+ * gas/aarch64/ldst-reg-imm-pre-ind.d: New file.
+ * gas/aarch64/ldst-reg-imm-pre-ind.s: New file.
+ * gas/aarch64/ldst-reg-pair.d: New file.
+ * gas/aarch64/ldst-reg-pair.s: New file.
+ * gas/aarch64/ldst-reg-reg-offset.d: New file.
+ * gas/aarch64/ldst-reg-reg-offset.s: New file.
+ * gas/aarch64/ldst-reg-uns-imm.d: New file.
+ * gas/aarch64/ldst-reg-uns-imm.s: New file.
+ * gas/aarch64/ldst-reg-unscaled-imm.d: New file.
+ * gas/aarch64/ldst-reg-unscaled-imm.s: New file.
+ * gas/aarch64/legacy_reg_names.d: New file.
+ * gas/aarch64/legacy_reg_names.l: New file.
+ * gas/aarch64/legacy_reg_names.s: New file.
+ * gas/aarch64/mapmisc.d: New file.
+ * gas/aarch64/mapmisc.dat: New file.
+ * gas/aarch64/mapmisc.s: New file.
+ * gas/aarch64/mapping.d: New file.
+ * gas/aarch64/mapping.s: New file.
+ * gas/aarch64/mapping2.d: New file.
+ * gas/aarch64/mapping2.s: New file.
+ * gas/aarch64/mapping3.d: New file.
+ * gas/aarch64/mapping3.s: New file.
+ * gas/aarch64/mapping4.d: New file.
+ * gas/aarch64/mapping4.s: New file.
+ * gas/aarch64/mov-no-aliases.d: New file.
+ * gas/aarch64/mov.d: New file.
+ * gas/aarch64/mov.s: New file.
+ * gas/aarch64/movi.d: New file.
+ * gas/aarch64/movi.s: New file.
+ * gas/aarch64/msr.d: New file.
+ * gas/aarch64/msr.s: New file.
+ * gas/aarch64/neon-fp-cvt-int.d: New file.
+ * gas/aarch64/neon-fp-cvt-int.s: New file.
+ * gas/aarch64/neon-frint.d: New file.
+ * gas/aarch64/neon-frint.s: New file.
+ * gas/aarch64/neon-ins.d: New file.
+ * gas/aarch64/neon-ins.s: New file.
+ * gas/aarch64/neon-not.d: New file.
+ * gas/aarch64/neon-not.s: New file.
+ * gas/aarch64/neon-vfp-reglist-post.d: New file.
+ * gas/aarch64/neon-vfp-reglist-post.s: New file.
+ * gas/aarch64/neon-vfp-reglist.d: New file.
+ * gas/aarch64/neon-vfp-reglist.s: New file.
+ * gas/aarch64/no-aliases.d: New file.
+ * gas/aarch64/optional.d: New file.
+ * gas/aarch64/optional.s: New file.
+ * gas/aarch64/programmer-friendly.d: New file.
+ * gas/aarch64/programmer-friendly.s: New file.
+ * gas/aarch64/reloc-data.d: New file.
+ * gas/aarch64/reloc-data.s: New file.
+ * gas/aarch64/reloc-insn.d: New file.
+ * gas/aarch64/reloc-insn.s: New file.
+ * gas/aarch64/shifted.d: New file.
+ * gas/aarch64/shifted.s: New file.
+ * gas/aarch64/symbol.d: New file.
+ * gas/aarch64/symbol.s: New file.
+ * gas/aarch64/sysreg-1.d: New file.
+ * gas/aarch64/sysreg-1.s: New file.
+ * gas/aarch64/sysreg.d: New file.
+ * gas/aarch64/sysreg.s: New file.
+ * gas/aarch64/system.d: New file.
+ * gas/aarch64/system.s: New file.
+ * gas/aarch64/tlbi_op.d: New file.
+ * gas/aarch64/tlbi_op.s: New file.
+ * gas/aarch64/tls.d: New file.
+ * gas/aarch64/tls.s: New file.
+ * gas/aarch64/verbose-error.d: New file.
+ * gas/aarch64/verbose-error.l: New file.
+ * gas/aarch64/verbose-error.s: New file.
+
2012-07-30 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/inval-equ-2.l: Updated.
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * dis-asm.h (print_insn_aarch64): New declaration.
+ (print_aarch64_disassembler_options): New declaration.
+ (aarch64_symbol_is_valid): New declaration.
+
2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
Dr David Alan Gilbert <dave@treblig.org>
target address. Return number of octets processed. */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
+extern int print_insn_aarch64 (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);
extern int print_insn_bfin (bfd_vma, disassemble_info *);
extern disassembler_ftype arc_get_disassembler (void *);
extern disassembler_ftype cris_get_disassembler (bfd *);
+extern void print_aarch64_disassembler_options (FILE *);
extern void print_i386_disassembler_options (FILE *);
extern void print_mips_disassembler_options (FILE *);
extern void print_ppc_disassembler_options (FILE *);
extern int get_arm_regname_num_options (void);
extern int set_arm_regname_option (int);
extern int get_arm_regnames (int, const char **, const char **, const char *const **);
+extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
extern void disassemble_init_powerpc (struct disassemble_info *);
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h: New file.
+ * common.h (EM_res183): Rename to EM_AARCH64.
+ (EM_res184): Rename to EM_ARM184.
+
2012-06-28 Iain Sandoe <iain@codesourcery.com>
* common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE,
START_RELOC_NUMBERS (elf_aarch64_reloc_type)
-/* Null relocations. */
+/* Null relocations. */
RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */
FAKE_RELOC (R_AARCH64_static_min, 256)
RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */
-/* Basic data relocations. */
+/* Basic data relocations. */
/* .xword: (S+A) */
RELOC_NUMBER (R_AARCH64_ABS64, 257)
RELOC_NUMBER (R_AARCH64_PREL16, 262)
/* Group relocations to create a 16, 32, 48 or 64 bit
- unsigned data or abs address inline. */
+ unsigned data or abs address inline. */
/* MOV[ZK]: ((S+A) >> 0) & 0xffff */
RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0, 263)
/* Group relocations to create high part of a 16, 32, 48 or 64 bit
signed data or abs address inline. Will change instruction
- to MOVN or MOVZ depending on sign of calculated value. */
+ to MOVN or MOVZ depending on sign of calculated value. */
/* MOV[ZN]: ((S+A) >> 0) & 0xffff */
RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270)
RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272)
/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
- addresses: PG(x) is (x & ~0xfff). */
+ addresses: PG(x) is (x & ~0xfff). */
/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273)
/* LD/ST8: (S+A) & 0xfff */
RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278)
-/* Relocations for control-flow instructions. */
+/* Relocations for control-flow instructions. */
-/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff. */
+/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff */
RELOC_NUMBER (R_AARCH64_TSTBR14, 279)
-/* B.cond: ((S+A-P) >> 2) & 0x7ffff. */
+/* B.cond: ((S+A-P) >> 2) & 0x7ffff */
RELOC_NUMBER (R_AARCH64_CONDBR19, 280)
/* 281 unused */
-/* B: ((S+A-P) >> 2) & 0x3ffffff. */
+/* B: ((S+A-P) >> 2) & 0x3ffffff */
RELOC_NUMBER (R_AARCH64_JUMP26, 282)
-/* BL: ((S+A-P) >> 2) & 0x3ffffff. */
+/* BL: ((S+A-P) >> 2) & 0x3ffffff */
RELOC_NUMBER (R_AARCH64_CALL26, 283)
/* LD/ST16: (S+A) & 0xffe */
#define EM_L1OM 180 /* Intel L1OM */
#define EM_K1OM 181 /* Intel K1OM */
#define EM_INTEL182 182 /* Reserved by Intel */
-#define EM_res183 183 /* Reserved by ARM */
-#define EM_res184 184 /* Reserved by ARM */
+#define EM_AARCH64 183 /* ARM 64-bit architecture */
+#define EM_ARM184 184 /* Reserved by ARM */
#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */
#define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */
#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h: New file.
+
2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h: Fix a typo in description.
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
-#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
+#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
-/* CPU-specific features. */
+/* CPU-specific features */
typedef unsigned long aarch64_feature_set;
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU) & (FEAT)) != 0)
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
- do \
- { \
- (TARG) = (F1) | (F2); \
- } \
- while (0)
+ do { \
+ (TARG) = (F1) | (F2); \
+ } while (0)
#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
- do \
- { \
- (TARG) = (F1) &~ (F2); \
- } \
- while (0)
+ do { \
+ (TARG) = (F1) &~ (F2); \
+ } while (0)
#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
\f
struct aarch64_name_value_pair
{
- const char * name;
+ const char *name;
aarch64_insn value;
};
/* Lane index; valid only when has_index is 1. */
unsigned index : 4;
} reglist;
- /* e.g. immediate or pc relative address offset. */
+ /* e.g. immediate or pc relative address offset. */
struct
{
int64_t value;
/* Encoding entrypoint. */
-extern int
-aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
- aarch64_insn *, aarch64_opnd_qualifier_t *,
- aarch64_operand_error *);
+int aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
+ aarch64_insn *, aarch64_opnd_qualifier_t *,
+ aarch64_operand_error *);
-extern const aarch64_opcode *
-aarch64_replace_opcode (struct aarch64_inst *,
- const aarch64_opcode *);
+const aarch64_opcode* aarch64_replace_opcode (struct aarch64_inst *,
+ const aarch64_opcode *);
/* Given the opcode enumerator OP, return the pointer to the corresponding
opcode entry. */
-extern const aarch64_opcode *
-aarch64_get_opcode (enum aarch64_op);
+const aarch64_opcode* aarch64_get_opcode (enum aarch64_op);
/* Generate the string representation of an operand. */
-extern void
-aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
- const aarch64_opnd_info *, int, int *, bfd_vma *);
+void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
+ const aarch64_opnd_info *, int, int *, bfd_vma *);
/* Miscellaneous interface. */
-extern int
-aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
+int aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
-extern aarch64_opnd_qualifier_t
+aarch64_opnd_qualifier_t
aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
const aarch64_opnd_qualifier_t, int);
-extern int
-aarch64_num_of_operands (const aarch64_opcode *);
+int aarch64_num_of_operands (const aarch64_opcode *);
-extern int
-aarch64_stack_pointer_p (const aarch64_opnd_info *);
-
-extern
+int aarch64_stack_pointer_p (const aarch64_opnd_info *);
int aarch64_zero_register_p (const aarch64_opnd_info *);
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
-extern unsigned char
-aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
-
-extern enum aarch64_operand_class
-aarch64_get_operand_class (enum aarch64_opnd);
-
-extern const char *
-aarch64_get_operand_name (enum aarch64_opnd);
-
-extern const char *
-aarch64_get_operand_desc (enum aarch64_opnd);
+unsigned char aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
+enum aarch64_operand_class aarch64_get_operand_class (enum aarch64_opnd);
+const char* aarch64_get_operand_name (enum aarch64_opnd);
+const char* aarch64_get_operand_desc (enum aarch64_opnd);
#ifdef DEBUG_AARCH64
extern int debug_dump;
-
-extern void
-aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
-
-#define DEBUG_TRACE(M, ...) \
- { \
- if (debug_dump) \
- aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
- }
-
-#define DEBUG_TRACE_IF(C, M, ...) \
- { \
- if (debug_dump && (C)) \
- aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
- }
+void aarch64_verbose (const char *str, ...)
+ __attribute__ ((format (printf, 1, 2)));
+#define DEBUG_TRACE(M, ...) { \
+ if (debug_dump) \
+ aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
+}
+#define DEBUG_TRACE_IF(C, M, ...) { \
+ if (debug_dump && (C)) \
+ aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
+}
#else /* !DEBUG_AARCH64 */
#define DEBUG_TRACE(M, ...) ;
#define DEBUG_TRACE_IF(C, M, ...) ;
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * configure.tgt: Add AArch64.
+ * emulparams/aarch64elf.sh: New file.
+ * emulparams/aarch64elfb.sh: New file.
+ * emulparams/aarch64linux.sh: New file.
+ * emulparams/aarch64linuxb.sh: New file.
+ * emultempl/aarch64elf.em: New file.
+ * NEWS: Mention the new feature.
+
2012-08-14 Nick Clifton <nickc@redhat.com>
* configure.in (ALL_LINGUGAS): Add uk.
ALL_EMULATIONS = $(ALL_EMULATION_SOURCES:.c=.@OBJEXT@)
ALL_64_EMULATION_SOURCES = \
+ eaarch64elf.c \
+ eaarch64elfb.c \
+ eaarch64linux.c \
+ eaarch64linuxb.c \
eelf32_x86_64.c \
eelf32_x86_64_nacl.c \
eelf64_aix.c \
$(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \
$(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)"
+eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)"
+eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)"
+eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)"
+eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
ALL_EMULATIONS = $(ALL_EMULATION_SOURCES:.c=.@OBJEXT@)
ALL_64_EMULATION_SOURCES = \
+ eaarch64elf.c \
+ eaarch64elfb.c \
+ eaarch64linux.c \
+ eaarch64linuxb.c \
eelf32_x86_64.c \
eelf32_x86_64_nacl.c \
eelf64_aix.c \
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/deffilep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64elfb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linuxb.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5ppc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5rs6.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixppc.Po@am__quote@
$(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \
$(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)"
+eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)"
+eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)"
+eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)"
+eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
Changes in 2.23:
+* Add support for 64-bit ARM architecture: AArch64
+
* Added SORT_NONE to the linker script language to disable section sorting.
* Add a linker-provided symbol when producing ELF output, '__ehdr_start'
# architecture variants should be kept together even if their names
# break the alpha sorting.
case "${targ}" in
+aarch64_be-*-elf) targ_emul=aarch64elfb
+ targ_extra_emuls="aarch64elf armelfb armelf" ;;
+aarch64-*-elf) targ_emul=aarch64elf
+ targ_extra_emuls="aarch64elfb armelf armelfb" ;;
+aarch64_be-*-linux*) targ_emul=aarch64linuxb
+ targ_extra_emuls="aarch64linux aarch64elfb aarch64elf armelfb_linux_eabi armelf_linux_eabi armelfb armelf" ;;
+aarch64-*-linux*) targ_emul=aarch64linux
+ targ_extra_emuls="aarch64linuxb aarch64elf aarch64elfb armelf_linux_eabi armelfb_linux_eabi armelf armelfb" ;;
alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
targ_emul=elf64alpha_fbsd
targ_extra_emuls="elf64alpha alpha"
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * ld-aarch64/aarch64-elf.exp: New file.
+ * ld-aarch64/aarch64.ld: New file.
+ * ld-aarch64/eh-frame-bar.s: New file.
+ * ld-aarch64/eh-frame-foo.s: New file.
+ * ld-aarch64/eh-frame.d: New file.
+ * ld-aarch64/emit-relocs-257-be.d: New file.
+ * ld-aarch64/emit-relocs-257.d: New file.
+ * ld-aarch64/emit-relocs-257.s: New file.
+ * ld-aarch64/emit-relocs-260-be.d: New file.
+ * ld-aarch64/emit-relocs-260.d: New file.
+ * ld-aarch64/emit-relocs-260.s: New file.
+ * ld-aarch64/emit-relocs-262.d: New file.
+ * ld-aarch64/emit-relocs-262.s: New file.
+ * ld-aarch64/emit-relocs-263.d: New file.
+ * ld-aarch64/emit-relocs-263.s: New file.
+ * ld-aarch64/emit-relocs-264.d: New file.
+ * ld-aarch64/emit-relocs-264.s: New file.
+ * ld-aarch64/emit-relocs-265.d: New file.
+ * ld-aarch64/emit-relocs-265.s: New file.
+ * ld-aarch64/emit-relocs-266.d: New file.
+ * ld-aarch64/emit-relocs-266.s: New file.
+ * ld-aarch64/emit-relocs-267.d: New file.
+ * ld-aarch64/emit-relocs-267.s: New file.
+ * ld-aarch64/emit-relocs-268.d: New file.
+ * ld-aarch64/emit-relocs-268.s: New file.
+ * ld-aarch64/emit-relocs-269.d: New file.
+ * ld-aarch64/emit-relocs-269.s: New file.
+ * ld-aarch64/emit-relocs-270-bad.d: New file.
+ * ld-aarch64/emit-relocs-270.d: New file.
+ * ld-aarch64/emit-relocs-270.s: New file.
+ * ld-aarch64/emit-relocs-271.d: New file.
+ * ld-aarch64/emit-relocs-271.s: New file.
+ * ld-aarch64/emit-relocs-272.d: New file.
+ * ld-aarch64/emit-relocs-272.s: New file.
+ * ld-aarch64/emit-relocs-273.d: New file.
+ * ld-aarch64/emit-relocs-273.s: New file.
+ * ld-aarch64/emit-relocs-274.d: New file.
+ * ld-aarch64/emit-relocs-274.s: New file.
+ * ld-aarch64/emit-relocs-275.d: New file.
+ * ld-aarch64/emit-relocs-275.s: New file.
+ * ld-aarch64/emit-relocs-276.d: New file.
+ * ld-aarch64/emit-relocs-276.s: New file.
+ * ld-aarch64/emit-relocs-277.d: New file.
+ * ld-aarch64/emit-relocs-277.s: New file.
+ * ld-aarch64/emit-relocs-278.d: New file.
+ * ld-aarch64/emit-relocs-278.s: New file.
+ * ld-aarch64/emit-relocs-279-bad.d: New file.
+ * ld-aarch64/emit-relocs-279.d: New file.
+ * ld-aarch64/emit-relocs-279.s: New file.
+ * ld-aarch64/emit-relocs-280.d: New file.
+ * ld-aarch64/emit-relocs-280.s: New file.
+ * ld-aarch64/emit-relocs-282.d: New file.
+ * ld-aarch64/emit-relocs-282.s: New file.
+ * ld-aarch64/emit-relocs-283.d: New file.
+ * ld-aarch64/emit-relocs-283.s: New file.
+ * ld-aarch64/emit-relocs-284.d: New file.
+ * ld-aarch64/emit-relocs-284.s: New file.
+ * ld-aarch64/emit-relocs-285.d: New file.
+ * ld-aarch64/emit-relocs-285.s: New file.
+ * ld-aarch64/emit-relocs-286-bad.d: New file.
+ * ld-aarch64/emit-relocs-286.d: New file.
+ * ld-aarch64/emit-relocs-286.s: New file.
+ * ld-aarch64/emit-relocs-287.d: New file.
+ * ld-aarch64/emit-relocs-287.s: New file.
+ * ld-aarch64/emit-relocs-299.d: New file.
+ * ld-aarch64/emit-relocs-299.s: New file.
+ * ld-aarch64/emit-relocs-311.d: New file.
+ * ld-aarch64/emit-relocs-311.s: New file.
+ * ld-aarch64/emit-relocs-312.d: New file.
+ * ld-aarch64/emit-relocs-312.s: New file.
+ * ld-aarch64/emit-relocs1.s: New file.
+ * ld-aarch64/farcall-b-none-function.d: New file.
+ * ld-aarch64/farcall-b-none-function.s: New file.
+ * ld-aarch64/farcall-b.d: New file.
+ * ld-aarch64/farcall-b.s: New file.
+ * ld-aarch64/farcall-back.d: New file.
+ * ld-aarch64/farcall-back.s: New file.
+ * ld-aarch64/farcall-bl-none-function.d: New file.
+ * ld-aarch64/farcall-bl-none-function.s: New file.
+ * ld-aarch64/farcall-bl.d: New file.
+ * ld-aarch64/farcall-bl.s: New file.
+ * ld-aarch64/farcall-section.d: New file.
+ * ld-aarch64/farcall-section.s: New file.
+ * ld-aarch64/limit-b.d: New file.
+ * ld-aarch64/limit-b.s: New file.
+ * ld-aarch64/limit-bl.d: New file.
+ * ld-aarch64/limit-bl.s: New file.
+ * ld-aarch64/relocs.ld: New file.
+ * ld-aarch64/tls-desc-ie.d: New file.
+ * ld-aarch64/tls-desc-ie.s: New file.
+ * ld-aarch64/tls-relax-all.d: New file.
+ * ld-aarch64/tls-relax-all.s: New file.
+ * ld-aarch64/tls-relax-gd-ie.d: New file.
+ * ld-aarch64/tls-relax-gd-ie.s: New file.
+ * ld-aarch64/tls-relax-gd-le.d: New file.
+ * ld-aarch64/tls-relax-gd-le.s: New file.
+ * ld-aarch64/tls-relax-gdesc-ie-2.d: New file.
+ * ld-aarch64/tls-relax-gdesc-ie-2.s: New file.
+ * ld-aarch64/tls-relax-gdesc-ie.d: New file.
+ * ld-aarch64/tls-relax-gdesc-ie.s: New file.
+ * ld-aarch64/tls-relax-gdesc-le-2.d: New file.
+ * ld-aarch64/tls-relax-gdesc-le-2.s: New file.
+ * ld-aarch64/tls-relax-gdesc-le.d: New file.
+ * ld-aarch64/tls-relax-gdesc-le.s: New file.
+ * ld-aarch64/tls-relax-ie-le-2.d: New file.
+ * ld-aarch64/tls-relax-ie-le-2.s: New file.
+ * ld-aarch64/tls-relax-ie-le-3.d: New file.
+ * ld-aarch64/tls-relax-ie-le-3.s: New file.
+ * ld-aarch64/tls-relax-ie-le.d: New file.
+ * ld-aarch64/tls-relax-ie-le.s: New file.
+ * ld-aarch64/weak-undefined.d: New file.
+ * ld-aarch64/weak-undefined.s: New file.
+ * ld-elf/binutils.exp (binutils_test): Add optional parameter
+ 'test_name'; change to construct 'test_name' from the 'prog_name'
+ and 'ld_options' only when "$test_name" == "".
+ * ld-elf/group8a.d (#notarget): Add AArch64.
+ * ld-elf/group8b.d (#notarget): Add AArch64.
+ * ld-elf/group9a.d (#notarget): Add AArch64.
+ * ld-elf/group9b.d (#notarget): Add AArch64.
+ * ld-elf/pr12851.d (#notarget): Add AArch64.
+ * ld-elf/pr12975.d (#notarget): Add AArch64.
+ * ld-elf/pr13177.d (#notarget): Add AArch64.
+ * ld-elf/pr13195.d (#notarget): Add AArch64.
+ * ld-elfvers/vers.exp: Add AArch64.
+ * ld-shared/shared.exp: Add AArch64.
+ * ld-srec/srec.exp: Add AArch64.
+ * lib/ld-lib.exp: Add AArch64.
+
2012-07-26 Meador Inge <meadori@codesourcery.com>
PR ld/14397
return
}
-proc binutils_test { prog_name ld_options test } {
+# The optional test_name argument provides a mechanism for the caller
+# to hardwire the test name. This is important if ld_options contains
+# absolute path names because the default test name is constructed
+# from the prog_name and ld_options and we do not want absolute paths
+# to appear in the test_name.
+proc binutils_test { prog_name ld_options test {test_name ""}} {
global as
global ld
global READELF
global link_output
eval set prog \$$prog_name
- set test_name "$prog_name $ld_options ($test)"
+
+ if { "$test_name" == "" } {
+ set test_name "$prog_name $ld_options ($test)"
+ }
if { ![ld_assemble $as $srcdir/$subdir/$test.s tmpdir/$test.o ] } {
unresolved "$test_name"
binutils_test objcopy "-z relro -shared" relro2
}
-binutils_test strip "-T ${srcdir}/${subdir}/lma.lnk" lma
+binutils_test strip "-T ${srcdir}/${subdir}/lma.lnk" lma "strip -T lma.lnk"
set tls_tests { "tdata1" "tdata2" }
# hppa64 has its own .tbss section, with different flags.
#source: group8.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group8.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group9.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group9.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: start.s
#ld: --gc-sections
#readelf: -s --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared -version-script pr12975.t
#readelf: -s --wide
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared
#readelf: -s -D --wide
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared -version-script pr13195.t
#readelf: -s --wide -D
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
&& ![istarget sparc*-*-elf]
&& ![istarget sparc*-*-solaris2*]
&& ![istarget sparc*-*-linux*]
+ && ![istarget aarch64*-*-linux*]
&& ![istarget arm*-*-linux*]
&& ![istarget mips*-*-linux*]
&& ![istarget alpha*-*-linux*]
&& ![istarget rs6000*-*-aix*] \
&& ![istarget powerpc*-*-aix*] \
&& ![istarget s390*-*-linux*] \
+ && ![istarget aarch64*-*-linux*] \
&& ![istarget x86_64-*-linux*] } {
return
}
setup_xfail "sh64*-*-*"
}
- if {[istarget arm*-*-*]} {
- # ARM targets cannot convert format in the linker
+ if {[istarget aarch64*-*-*] || \
+ [istarget arm*-*-*]} {
+ # ARM targets cannot convert format in the linker
# using the --oformat command line switch
+ setup_xfail "aarch64-*-*"
+ setup_xfail "aarch64_be-*-*"
setup_xfail "arm*-*-*"
}
if {![info exists gc_sections_available_saved]} {
# Some targets don't support gc-sections despite whatever's
# advertised by ld's options.
- if {[istarget arc-*-*]
+ if {[istarget aarch64*-*-*]
+ || [istarget arc-*-*]
|| [istarget d30v-*-*]
|| [istarget dlx-*-*]
|| [istarget i960-*-*]
+2012-08-16 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * aarch64-asm.c: New file.
+ * aarch64-asm.h: New file.
+ * aarch64-dis.c: New file.
+ * aarch64-dis.h: New file.
+ * aarch64-gen.c: New file.
+ * aarch64-opc.c: New file.
+ * aarch64-opc.h: New file.
+ * aarch64-tbl.h: New file.
+ * configure.in: Add AArch64.
+ * configure: Regenerate.
+ * disassemble.c: Add AArch64.
+ * aarch64-asm-2.c: New file (automatically generated).
+ * aarch64-dis-2.c: New file (automatically generated).
+ * aarch64-opc-2.c: New file (automatically generated).
+ * po/POTFILES.in: Regenerate.
+
2012-08-09 Nick Clifton <nickc@redhat.com>
* po/vi.po: Updated Vietnamese translation.
# Header files.
HFILES = \
+ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
# C source files that correspond to .o's ending up in libopcodes
# for all machines.
TARGET_LIBOPCODES_CFILES = \
+ aarch64-asm.c \
+ aarch64-asm-2.c \
+ aarch64-dis.c \
+ aarch64-dis-2.c \
+ aarch64-opc.c \
+ aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
arc-dis.c \
# C source files that correspond to .o's.
CFILES = \
$(LIBOPCODES_CFILES) \
+ aarch64-gen.c \
i386-gen.c \
ia64-asmtab.c \
ia64-gen.c \
$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
- s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
- opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+ ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+ $(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
$(srcdir)/rl78-decode.c \
$(srcdir)/rx-decode.c
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+ $(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+ $(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+ $(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
# Header files.
HFILES = \
+ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
# C source files that correspond to .o's ending up in libopcodes
# for all machines.
TARGET_LIBOPCODES_CFILES = \
+ aarch64-asm.c \
+ aarch64-asm-2.c \
+ aarch64-dis.c \
+ aarch64-dis-2.c \
+ aarch64-opc.c \
+ aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
arc-dis.c \
# C source files that correspond to .o's.
CFILES = \
$(LIBOPCODES_CFILES) \
+ aarch64-gen.c \
i386-gen.c \
ia64-asmtab.c \
ia64-gen.c \
@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
@CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
- s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
- opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+ ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+ $(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
$(srcdir)/rl78-decode.c \
$(srcdir)/rx-decode.c
distclean-compile:
-rm -f *.tab.c
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@
$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+ $(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+ $(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+ $(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
const aarch64_field *field;
enum aarch64_field_kind kind;
va_list va;
-
va_start (va, mask);
num = va_arg (va, uint32_t);
assert (num <= 5);
/* Operand inserters. */
/* Insert register number. */
-const char *
+const char*
aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, info->reg.regno, 0);
- return NULL;
+ return 0;
}
/* Insert register number, index and/or other data for SIMD register element
operand, e.g. the last source operand in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
-const char *
+const char*
aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst)
{
assert (0);
}
}
- return NULL;
+ return 0;
}
/* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
-const char *
+const char*
aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
insert_field (self->fields[0], code, info->reglist.first_regno, 0);
/* len */
insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
- return NULL;
+ return 0;
}
/* Insert Rt and opcode fields for a register list operand, e.g. Vt
in AdvSIMD load/store instructions. */
-const char *
+const char*
aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst)
}
insert_field (FLD_opcode, code, value, 0);
- return NULL;
+ return 0;
}
/* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
single structure to all lanes instructions. */
-const char *
+const char*
aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst)
value = (aarch64_insn) 1;
insert_field (FLD_S, code, value, 0);
- return NULL;
+ return 0;
}
/* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
operand e.g. Vt in AdvSIMD load/store single element instructions. */
-const char *
+const char*
aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
insert_field_2 (&field, code, opcodeh2, 0);
- return NULL;
+ return 0;
}
/* Insert fields immh:immb and/or Q for e.g. the shift immediate in
SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
or SSHR <V><d>, <V><n>, #<shift>. */
-const char *
+const char*
aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst)
imm = info->imm.value + (8 << (unsigned)val);
insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
- return NULL;
+ return 0;
}
/* Insert fields for e.g. the immediate operands in
BFM <Wd>, <Wn>, #<immr>, #<imms>. */
-const char *
+const char*
aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
else
/* e.g. TBZ b5:b40. */
insert_fields (code, imm, 0, 2, self->fields[1], self->fields[0]);
- return NULL;
+ return 0;
}
/* Insert immediate and its shift amount for e.g. the last operand in
MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
-const char *
+const char*
aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
aarch64_ins_imm (self, info, code, inst);
/* hw */
insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
- return NULL;
+ return 0;
}
/* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
-const char *
+const char*
aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
if (kind == AARCH64_MOD_NONE)
- return NULL;
+ return 0;
/* shift amount partially in cmode */
assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
}
insert_field_2 (&field, code, amount, 0);
- return NULL;
+ return 0;
}
/* Insert #<fbits> for the immediate operand in fp fix-point instructions,
e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
-const char *
+const char*
aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, 64 - info->imm.value, 0);
- return NULL;
+ return 0;
}
/* Insert arithmetic immediate for e.g. the last operand in
SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
-const char *
+const char*
aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, value, 0);
/* imm12 (unsigned) */
insert_field (self->fields[1], code, info->imm.value, 0);
- return NULL;
+ return 0;
}
/* Insert logical/bitmask immediate for e.g. the last operand in
ORR <Wd|WSP>, <Wn>, #<imm>. */
-const char *
+const char*
aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
self->fields[0]);
- return NULL;
+ return 0;
}
/* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
-const char *
+const char*
aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst)
{
insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
}
- return NULL;
+ return 0;
}
/* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
-const char *
+const char*
aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* Rn */
insert_field (FLD_Rn, code, info->addr.base_regno, 0);
- return NULL;
+ return 0;
}
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-const char *
+const char*
aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
S = info->shifter.operator_present && info->shifter.amount_present;
insert_field (FLD_S, code, S, 0);
- return NULL;
+ return 0;
}
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
-const char *
+const char*
aarch64_ins_addr_simm (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst)
insert_field (self->fields[1], code, 1, 0);
}
- return NULL;
+ return 0;
}
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
-const char *
+const char*
aarch64_ins_addr_uimm12 (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
-
/* Rn */
insert_field (self->fields[0], code, info->addr.base_regno, 0);
/* uimm12 */
insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
- return NULL;
+ return 0;
}
/* Encode the address operand for e.g.
LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
-const char *
+const char*
aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
else
insert_field (FLD_Rm, code, 0x1f, 0);
- return NULL;
+ return 0;
}
/* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
-const char *
+const char*
aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* cond */
insert_field (FLD_cond, code, info->cond->value, 0);
- return NULL;
+ return 0;
}
/* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
-const char *
+const char*
aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
/* op0:op1:CRn:CRm:op2 */
insert_fields (code, info->sysreg, inst->opcode->mask, 5,
FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
- return NULL;
+ return 0;
}
/* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
-const char *
+const char*
aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
/* op1:op2 */
insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
FLD_op2, FLD_op1);
- return NULL;
+ return 0;
}
/* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
-const char *
+const char*
aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
/* op1:CRn:CRm:op2 */
insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
- return NULL;
+ return 0;
}
/* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
-const char *
+const char*
aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* CRm */
insert_field (FLD_CRm, code, info->barrier->value, 0);
- return NULL;
+ return 0;
}
/* Encode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
-const char *
+const char*
aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* prfop in Rt */
insert_field (FLD_Rt, code, info->prfop->value, 0);
- return NULL;
+ return 0;
}
/* Encode the extended register operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-const char *
+const char*
aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
/* imm3 */
insert_field (FLD_imm3, code, info->shifter.amount, 0);
- return NULL;
+ return 0;
}
/* Encode the shifted register operand for e.g.
SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
-const char *
+const char*
aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
/* imm6 */
insert_field (FLD_imm6, code, info->shifter.amount, 0);
- return NULL;
+ return 0;
}
/* Miscellaneous encoding functions. */
convert_bfx_to_bfm (aarch64_inst *inst)
{
int64_t lsb, width;
-
/* Convert the operand. */
lsb = inst->operands[2].imm.value;
width = inst->operands[3].imm.value;
convert_bfi_to_bfm (aarch64_inst *inst)
{
int64_t lsb, width;
-
/* Convert the operand. */
lsb = inst->operands[2].imm.value;
width = inst->operands[3].imm.value;
convert_lsl_to_ubfm (aarch64_inst *inst)
{
int64_t shift = inst->operands[2].imm.value;
-
if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
{
inst->operands[2].imm.value = (32 - shift) & 0x1f;
convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
{
const aarch64_opcode *alias = inst->opcode;
-
if ((alias->flags & F_CONV) == 0)
goto convert_to_real_return;
const aarch64_field *field;
enum aarch64_field_kind kind;
va_list va;
-
va_start (va, mask);
num = va_arg (va, uint32_t);
assert (num <= 5);
sign_extend (aarch64_insn value, unsigned i)
{
uint32_t ret = value;
-
assert (i < 32);
if ((value >> i) & 0x1)
{
get_vreg_qualifier_from_value (aarch64_insn value)
{
enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
-
assert (value <= 0x8
&& aarch64_get_qualifier_standard_value (qualifier) == value);
return qualifier;
get_sreg_qualifier_from_value (aarch64_insn value)
{
enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
-
assert (value <= 0x4
&& aarch64_get_qualifier_standard_value (qualifier) == value);
return qualifier;
info->reglane.regno = extract_field (self->fields[0], code,
inst->opcode->mask);
- /* Index and/or type. */
+ /* index and/or type */
if (inst->opcode->iclass == asisdone
|| inst->opcode->iclass == asimdins)
{
}
else
{
- /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+ /* index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
/* Need information in other operand(s) to help decoding. */
return 0;
/* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
- (in other words, right rotated by R), then replicated. */
+ (in other words, right rotated by R), then replicated. */
if (N != 0)
{
simd_size = 64;
suffix. */
char name[8], *ptr;
size_t len;
-
+
ptr = strchr (inst->opcode->name, '.');
assert (ptr && inst->cond);
len = ptr - inst->opcode->name;
if (((word >> 21) & 0x3ff) == 1)
{
- /* RESERVED for ALES. */
+ /* RESERVED for ALES. */
assert (ret != ERR_OK);
ret = ERR_NYI;
}
/* Call divide_table_1 to divide the all the opcodes and thus create the
decoding decision tree. */
-static struct bittree *
+static struct bittree*
divide_table (void)
{
struct bittree *bittree = new_bittree_node ();
/* Read in all of the tables, create the decoding decision tree and return
the tree root. */
-static struct bittree *
+static struct bittree*
initialize_decoder_tree (void)
{
int i;
return aarch64_operands[type].op_class;
}
-const char *
+const char*
aarch64_get_operand_name (enum aarch64_opnd type)
{
return aarch64_operands[type].name;
/* Get operand description string.
This is usually for the diagnosis purpose. */
-const char *
+const char*
aarch64_get_operand_desc (enum aarch64_opnd type)
{
return aarch64_operands[type].desc;
{{"nv"}, 0xf},
};
-const aarch64_cond *
+const aarch64_cond*
get_cond_from_value (aarch64_insn value)
{
assert (value < 16);
return &aarch64_conds[(unsigned int) value];
}
-const aarch64_cond *
+const aarch64_cond*
get_inverted_cond (const aarch64_cond *cond)
{
return &aarch64_conds[cond->value ^ 0x1];
if (is32)
{
/* Allow all zeros or all ones in top 32-bits, so that
- constant expressions like ~1 are permitted. */
+ constant expressions like ~1 are permitted. */
if (value >> 32 != 0 && value >> 32 != 0xffffffff)
return 0xffffffff;
/* Replicate the 32 lower bits to the 32 upper bits. */
{
case OP_MOV_IMM_WIDEN:
imm = ~imm;
- /* Fall through... */
+ /* Fall through... */
case OP_MOV_IMM_WIDE:
if (!aarch64_wide_constant_p (imm, is32, NULL))
{
ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
+ bfd_aarch64_arch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
+ bfd_aarch64_arch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
#include "dis-asm.h"
#ifdef ARCH_all
+#define ARCH_aarch64
#define ARCH_alpha
#define ARCH_arc
#define ARCH_arm
{
/* If you add a case to this table, also add it to the
ARCH_all definition right above this function. */
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ disassemble = print_insn_aarch64;
+ break;
+#endif
#ifdef ARCH_alpha
case bfd_arch_alpha:
disassemble = print_insn_alpha;
disassembler_usage (stream)
FILE * stream ATTRIBUTE_UNUSED;
{
+#ifdef ARCH_aarch64
+ print_aarch64_disassembler_options (stream);
+#endif
#ifdef ARCH_arm
print_arm_disassembler_options (stream);
#endif
switch (info->arch)
{
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ info->symbol_is_valid = aarch64_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
#ifdef ARCH_arm
case bfd_arch_arm:
info->symbol_is_valid = arm_symbol_is_valid;
projects / thirdparty / binutils-gdb.git / commitdiff
