drm/tidss: Update infrastructure to support K3 DSS cut-down versions

SoCs like AM62Lx support cut-down version of K3 DSS where although same
register space is supported as in other K3 DSS supported SoCs such as
AM65x, AM62x, AM62Ax but some of the resources such as planes and
corresponding register spaces are truncated.

For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding
register spaces for other video pipelines need to be skipped.

To add a generic support for future SoCs where one or more video pipelines
can get truncated from the parent register space, move the video plane
related information to vid_info struct which will also have a field to
indicate hardware index of each of the available video planes, so that
driver only maps and programs those video pipes and skips the unavailable
ones.

While at it, also change the num_planes field in the features structure to
num_vid so that all places in code which use vid_info structure are
highlighted in the code.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://lore.kernel.org/r/20250507180631.874930-3-devarsht@ti.com
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c
index 94f8e3178df58a7f4730459ea112fb109f7a674a..a2f40a5c77030e1efdfbba613e9a2e7e0699aa9c 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss,
            !to_tidss_crtc_state(cstate)->plane_pos_changed)
                return;
 
-       for (layer = 0; layer < tidss->feat->num_planes; layer++) {
+       for (layer = 0; layer < tidss->feat->num_vids ; layer++) {
                struct drm_plane_state *pstate;
                struct drm_plane *plane;
                bool layer_active = false;
@@ -271,7 +271,7 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,
         * another videoport, the DSS will report sync lost issues. Disable all
         * the layers here as a work-around.
         */
-       for (u32 layer = 0; layer < tidss->feat->num_planes; layer++)
+       for (u32 layer = 0; layer < tidss->feat->num_vids; layer++)
                dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
                                       false);
 

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index cacb5f3d8085b40a04deaaa450385753df4bc2ab..774c608c88b50977ca0bd7089a6cefad94fc7c72 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -103,9 +103,16 @@ const struct dispc_features dispc_k2g_feats = {
                },
        },
 
-       .num_planes = 1,
-       .vid_name = { "vid1" },
-       .vid_lite = { false },
+       .num_vids = 1,
+
+       .vid_info = {
+               {
+                       .name = "vid1",
+                       .is_lite = false,
+                       .hw_id = 0,
+               },
+       },
+
        .vid_order = { 0 },
 };
 
@@ -178,11 +185,22 @@ const struct dispc_features dispc_am65x_feats = {
                },
        },
 
-       .num_planes = 2,
+       .num_vids = 2,
        /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
-       .vid_name = { "vid", "vidl1" },
-       .vid_lite = { false, true, },
-       .vid_order = { 1, 0 },
+       .vid_info = {
+               {
+                       .name = "vid",
+                       .is_lite = false,
+                       .hw_id = 0,
+               },
+               {
+                       .name = "vidl1",
+                       .is_lite = true,
+                       .hw_id = 1,
+               },
+       },
+
+       .vid_order = {1, 0},
 };
 
 static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
@@ -267,9 +285,32 @@ const struct dispc_features dispc_j721e_feats = {
                        .gamma_type = TIDSS_GAMMA_10BIT,
                },
        },
-       .num_planes = 4,
-       .vid_name = { "vid1", "vidl1", "vid2", "vidl2" },
-       .vid_lite = { 0, 1, 0, 1, },
+
+       .num_vids = 4,
+
+       .vid_info = {
+               {
+                       .name = "vid1",
+                       .is_lite = false,
+                       .hw_id = 0,
+               },
+               {
+                       .name = "vidl1",
+                       .is_lite = true,
+                       .hw_id = 1,
+               },
+               {
+                       .name = "vid2",
+                       .is_lite = false,
+                       .hw_id = 2,
+               },
+               {
+                       .name = "vidl2",
+                       .is_lite = true,
+                       .hw_id = 3,
+               },
+       },
+
        .vid_order = { 1, 3, 0, 2 },
 };
 
@@ -315,11 +356,23 @@ const struct dispc_features dispc_am625_feats = {
                },
        },
 
-       .num_planes = 2,
+       .num_vids = 2,
+
        /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
-       .vid_name = { "vid", "vidl1" },
-       .vid_lite = { false, true, },
-       .vid_order = { 1, 0 },
+       .vid_info = {
+               {
+                       .name = "vid",
+                       .is_lite = false,
+                       .hw_id = 0,
+               },
+               {
+                       .name = "vidl1",
+                       .is_lite = true,
+                       .hw_id = 1,
+               }
+       },
+
+       .vid_order = {1, 0},
 };
 
 const struct dispc_features dispc_am62a7_feats = {
@@ -369,11 +422,22 @@ const struct dispc_features dispc_am62a7_feats = {
                },
        },
 
-       .num_planes = 2,
-       /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
-       .vid_name = { "vid", "vidl1" },
-       .vid_lite = { false, true, },
-       .vid_order = { 1, 0 },
+       .num_vids = 2,
+
+       .vid_info = {
+               {
+                       .name = "vid",
+                       .is_lite = false,
+                       .hw_id = 0,
+               },
+               {
+                       .name = "vidl1",
+                       .is_lite = true,
+                       .hw_id = 1,
+               }
+       },
+
+       .vid_order = {1, 0},
 };
 
 static const u16 *dispc_common_regmap;
@@ -734,7 +798,8 @@ static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
                                               u32 hw_plane)
 {
-       u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+       u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_id));
 
        return dispc_vid_irq_from_raw(stat, hw_plane);
 }
@@ -742,9 +807,10 @@ static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
                                         u32 hw_plane, dispc_irq_t vidstat)
 {
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
        u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 
-       dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
+       dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_id), stat);
 }
 
 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
@@ -766,7 +832,8 @@ static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
                                               u32 hw_plane)
 {
-       u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+       u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_id));
 
        return dispc_vid_irq_from_raw(stat, hw_plane);
 }
@@ -774,9 +841,10 @@ static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
                                       u32 hw_plane, dispc_irq_t vidstat)
 {
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
        u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 
-       dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
+       dispc_write(dispc, DISPC_VID_IRQENABLE(hw_id), stat);
 }
 
 static
@@ -788,7 +856,8 @@ void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
                if (clearmask & DSS_IRQ_VP_MASK(i))
                        dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
        }
-       for (i = 0; i < dispc->feat->num_planes; ++i) {
+
+       for (i = 0; i < dispc->feat->num_vids; ++i) {
                if (clearmask & DSS_IRQ_PLANE_MASK(i))
                        dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
        }
@@ -809,7 +878,7 @@ dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
        for (i = 0; i < dispc->feat->num_vps; ++i)
                status |= dispc_k3_vp_read_irqstatus(dispc, i);
 
-       for (i = 0; i < dispc->feat->num_planes; ++i)
+       for (i = 0; i < dispc->feat->num_vids; ++i)
                status |= dispc_k3_vid_read_irqstatus(dispc, i);
 
        dispc_k3_clear_irqstatus(dispc, status);
@@ -825,7 +894,7 @@ static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
        for (i = 0; i < dispc->feat->num_vps; ++i)
                enable |= dispc_k3_vp_read_irqenable(dispc, i);
 
-       for (i = 0; i < dispc->feat->num_planes; ++i)
+       for (i = 0; i < dispc->feat->num_vids; ++i)
                enable |= dispc_k3_vid_read_irqenable(dispc, i);
 
        return enable;
@@ -851,12 +920,15 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc,
                        main_disable |= BIT(i);         /* VP IRQ */
        }
 
-       for (i = 0; i < dispc->feat->num_planes; ++i) {
+       for (i = 0; i < dispc->feat->num_vids; ++i) {
+               u32 hw_id = dispc->feat->vid_info[i].hw_id;
+
                dispc_k3_vid_set_irqenable(dispc, i, mask);
+
                if (mask & DSS_IRQ_PLANE_MASK(i))
-                       main_enable |= BIT(i + 4);      /* VID IRQ */
+                       main_enable |= BIT(hw_id + 4);  /* VID IRQ */
                else
-                       main_disable |= BIT(i + 4);     /* VID IRQ */
+                       main_disable |= BIT(hw_id + 4); /* VID IRQ */
        }
 
        if (main_enable)
@@ -1358,8 +1430,10 @@ static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
                                      u32 hw_plane, u32 hw_videoport,
                                      u32 x, u32 y, u32 layer)
 {
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       hw_plane, 4, 1);
+                       hw_id, 4, 1);
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
                        x, 17, 6);
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
@@ -1370,8 +1444,10 @@ static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
                                      u32 hw_plane, u32 hw_videoport,
                                      u32 x, u32 y, u32 layer)
 {
+       u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       hw_plane, 4, 1);
+                       hw_id, 4, 1);
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
                        x, 13, 0);
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
@@ -2025,7 +2101,7 @@ int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
                      const struct drm_plane_state *state,
                      u32 hw_videoport)
 {
-       bool lite = dispc->feat->vid_lite[hw_plane];
+       bool lite = dispc->feat->vid_info[hw_plane].is_lite;
        u32 fourcc = state->fb->format->format;
        bool need_scaling = state->src_w >> 16 != state->crtc_w ||
                state->src_h >> 16 != state->crtc_h;
@@ -2096,7 +2172,7 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
                       const struct drm_plane_state *state,
                       u32 hw_videoport)
 {
-       bool lite = dispc->feat->vid_lite[hw_plane];
+       bool lite = dispc->feat->vid_info[hw_plane].is_lite;
        u32 fourcc = state->fb->format->format;
        u16 cpp = state->fb->format->cpp[0];
        u32 fb_width = state->fb->pitches[0] / cpp;
@@ -2210,7 +2286,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
        /* MFLAG_START = MFLAGNORMALSTARTMODE */
        REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
 
-       for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
+       for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
                u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
                u32 thr_low, thr_high;
                u32 mflag_low, mflag_high;
@@ -2226,7 +2302,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
 
                dev_dbg(dispc->dev,
                        "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
-                       dispc->feat->vid_name[hw_plane],
+                       dispc->feat->vid_info[hw_plane].name,
                        size,
                        thr_high, thr_low,
                        mflag_high, mflag_low,
@@ -2265,7 +2341,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
        /* MFLAG_START = MFLAGNORMALSTARTMODE */
        REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
 
-       for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
+       for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
                u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
                u32 thr_low, thr_high;
                u32 mflag_low, mflag_high;
@@ -2281,7 +2357,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
 
                dev_dbg(dispc->dev,
                        "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
-                       dispc->feat->vid_name[hw_plane],
+                       dispc->feat->vid_info[hw_plane].name,
                        size,
                        thr_high, thr_low,
                        mflag_high, mflag_low,
@@ -2898,8 +2974,8 @@ int dispc_init(struct tidss_device *tidss)
        if (r)
                return r;
 
-       for (i = 0; i < dispc->feat->num_planes; i++) {
-               r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
+       for (i = 0; i < dispc->feat->num_vids; i++) {
+               r = dispc_iomap_resource(pdev, dispc->feat->vid_info[i].name,
                                         &dispc->base_vid[i]);
                if (r)
                        return r;

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index 086327d51a903f6af0b686695bb3611b249de2d8..72a0146e57d5fbd48f4049a975ca41fbb514b1ea 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -46,6 +46,12 @@ struct dispc_features_scaling {
        u32 xinc_max;
 };
 
+struct dispc_vid_info {
+       const char *name; /* Should match dt reg names */
+       u32 hw_id;
+       bool is_lite;
+};
+
 struct dispc_errata {
        bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */
 };
@@ -82,9 +88,8 @@ struct dispc_features {
        const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
        const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
        struct tidss_vp_feat vp_feat;
-       u32 num_planes;
-       const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
-       bool vid_lite[TIDSS_MAX_PLANES];
+       u32 num_vids;
+       struct dispc_vid_info vid_info[TIDSS_MAX_PLANES];
        u32 vid_order[TIDSS_MAX_PLANES];
 };
 

diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c
index f371518f869710426dc796964d87bf9a995ce82a..19432c08ec6bde610b6bea05c27710eb75035107 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_kms.c
+++ b/drivers/gpu/drm/tidss/tidss_kms.c
@@ -115,7 +115,7 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)
 
        const struct dispc_features *feat = tidss->feat;
        u32 max_vps = feat->num_vps;
-       u32 max_planes = feat->num_planes;
+       u32 max_planes = feat->num_vids;
 
        struct pipe pipes[TIDSS_MAX_PORTS];
        u32 num_pipes = 0;

diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c
index 719412e6c34604c32ebcaf4cc7c9731bceec8f1d..142ae81951a0916ccf7d3add1b83b011eca7f6b9 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_plane.c
+++ b/drivers/gpu/drm/tidss/tidss_plane.c
@@ -200,7 +200,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
        struct tidss_plane *tplane;
        enum drm_plane_type type;
        u32 possible_crtcs;
-       u32 num_planes = tidss->feat->num_planes;
+       u32 num_planes = tidss->feat->num_vids;
        u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
                               BIT(DRM_COLOR_YCBCR_BT709));
        u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |