--- /dev/null
+From b3fb22733ae61050f8d10a1d6a8af176c5c5db1a Mon Sep 17 00:00:00 2001
+From: Ondrej Zary <linux@rainbow-software.org>
+Date: Fri, 9 Mar 2018 23:22:04 +0100
+Subject: drm/i915: Disable LVDS on Radiant P845
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ondrej Zary <linux@rainbow-software.org>
+
+commit b3fb22733ae61050f8d10a1d6a8af176c5c5db1a upstream.
+
+Radiant P845 does not have LVDS, only VGA.
+
+Cc: stable@vger.kernel.org
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105468
+Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180309222204.4771-1-linux@rainbow-software.org
+(cherry picked from commit 7f7105f99b75aca4f8c2a748ed6b82c7f8be3293)
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -745,6 +745,14 @@ static const struct dmi_system_id intel_
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
+ },
+ },
++ {
++ .callback = intel_no_lvds_dmi_callback,
++ .ident = "Radiant P845",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
++ },
++ },
+
+ { } /* terminating entry */
+ };
--- /dev/null
+From c7e814628df65f424fe197dde73bfc67e4a244d7 Mon Sep 17 00:00:00 2001
+From: "Maciej W. Rozycki" <macro@mips.com>
+Date: Wed, 16 May 2018 16:39:58 +0100
+Subject: MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs
+
+From: Maciej W. Rozycki <macro@mips.com>
+
+commit c7e814628df65f424fe197dde73bfc67e4a244d7 upstream.
+
+Use 64-bit accesses for 64-bit floating-point general registers with
+PTRACE_PEEKUSR, removing the truncation of their upper halves in the
+FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
+access"), which inadvertently switched them to using 32-bit accesses.
+
+The PTRACE_POKEUSR side is fine as it's never been broken and continues
+using 64-bit accesses.
+
+Fixes: bbd426f542cb ("MIPS: Simplify FP context access")
+Signed-off-by: Maciej W. Rozycki <macro@mips.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: linux-mips@linux-mips.org
+Cc: <stable@vger.kernel.org> # 3.15+
+Patchwork: https://patchwork.linux-mips.org/patch/19334/
+Signed-off-by: James Hogan <jhogan@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/kernel/ptrace.c | 2 +-
+ arch/mips/kernel/ptrace32.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/kernel/ptrace.c
++++ b/arch/mips/kernel/ptrace.c
+@@ -713,7 +713,7 @@ long arch_ptrace(struct task_struct *chi
+ break;
+ }
+ #endif
+- tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
++ tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
+ break;
+ case PC:
+ tmp = regs->cp0_epc;
+--- a/arch/mips/kernel/ptrace32.c
++++ b/arch/mips/kernel/ptrace32.c
+@@ -107,7 +107,7 @@ long compat_arch_ptrace(struct task_stru
+ addr & 1);
+ break;
+ }
+- tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
++ tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
+ break;
+ case PC:
+ tmp = regs->cp0_epc;
selinux-kasan-slab-out-of-bounds-in-xattr_getsecurity.patch
cfg80211-further-limit-wiphy-names-to-64-bytes.patch
tcp-avoid-integer-overflows-in-tcp_rcv_space_adjust.patch
+mips-ptrace-fix-ptrace_peekusr-requests-for-64-bit-fgrs.patch
+drm-i915-disable-lvds-on-radiant-p845.patch