Fixes for 5.15

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.15/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch b/queue-5.15/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
new file mode 100644 (file)
index 0000000..3655dc9
--- /dev/null
+++ b/queue-5.15/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
@@ -0,0 +1,62 @@
+From 1d80e074cc1fc342fbe378d8fcb6b06773d07b0e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Jul 2023 11:10:16 +0800
+Subject: ALSA: hda: fix a possible null-pointer dereference due to data race
+ in snd_hdac_regmap_sync()
+
+From: Tuo Li <islituo@gmail.com>
+
+[ Upstream commit 1f4a08fed450db87fbb5ff5105354158bdbe1a22 ]
+
+The variable codec->regmap is often protected by the lock
+codec->regmap_lock when is accessed. However, it is accessed without
+holding the lock when is accessed in snd_hdac_regmap_sync():
+
+  if (codec->regmap)
+
+In my opinion, this may be a harmful race, because if codec->regmap is
+set to NULL right after the condition is checked, a null-pointer
+dereference can occur in the called function regcache_sync():
+
+  map->lock(map->lock_arg); --> Line 360 in drivers/base/regmap/regcache.c
+
+To fix this possible null-pointer dereference caused by data race, the
+mutex_lock coverage is extended to protect the if statement as well as the
+function call to regcache_sync().
+
+[ Note: the lack of the regmap_lock itself is harmless for the current
+  codec driver implementations, as snd_hdac_regmap_sync() is only for
+  PM runtime resume that is prohibited during the codec probe.
+  But the change makes the whole code more consistent, so it's merged
+  as is -- tiwai ]
+
+Reported-by: BassCheck <bass@buaa.edu.cn>
+Signed-off-by: Tuo Li <islituo@gmail.com>
+Link: https://lore.kernel.org/r/20230703031016.1184711-1-islituo@gmail.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/hda/hdac_regmap.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/sound/hda/hdac_regmap.c b/sound/hda/hdac_regmap.c
+index fe3587547cfec..39610a15bcc98 100644
+--- a/sound/hda/hdac_regmap.c
++++ b/sound/hda/hdac_regmap.c
+@@ -597,10 +597,9 @@ EXPORT_SYMBOL_GPL(snd_hdac_regmap_update_raw_once);
+  */
+ void snd_hdac_regmap_sync(struct hdac_device *codec)
+ {
+-      if (codec->regmap) {
+-              mutex_lock(&codec->regmap_lock);
++      mutex_lock(&codec->regmap_lock);
++      if (codec->regmap)
+               regcache_sync(codec->regmap);
+-              mutex_unlock(&codec->regmap_lock);
+-      }
++      mutex_unlock(&codec->regmap_lock);
+ }
+ EXPORT_SYMBOL_GPL(snd_hdac_regmap_sync);
+-- 
+2.40.1
+

diff --git a/queue-5.15/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch b/queue-5.15/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
new file mode 100644 (file)
index 0000000..324ee4b
--- /dev/null
+++ b/queue-5.15/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
@@ -0,0 +1,59 @@
+From 407239cb92d2317968f9e0008e2cb8a9419df64f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Jul 2023 10:17:51 +0800
+Subject: ALSA: hda/realtek: Add quirks for Unis H3C Desktop B760 & Q760
+
+From: dengxiang <dengxiang@nfschina.com>
+
+[ Upstream commit 73f1c75d5e6bd8ce2a887ef493a66ad1b16ed704 ]
+
+These models use NSIWAY amplifiers for internal speaker, but cannot put
+sound outside from these amplifiers. So eapd verbs are needed to initialize
+the amplifiers. They can be added during boot to get working sound out
+of internal speaker.
+
+Signed-off-by: dengxiang <dengxiang@nfschina.com>
+Link: https://lore.kernel.org/r/20230703021751.2945750-1-dengxiang@nfschina.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/patch_realtek.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index 965720b1d1b16..e335f3b5338f7 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -10809,6 +10809,7 @@ enum {
+       ALC897_FIXUP_HP_HSMIC_VERB,
+       ALC897_FIXUP_LENOVO_HEADSET_MODE,
+       ALC897_FIXUP_HEADSET_MIC_PIN2,
++      ALC897_FIXUP_UNIS_H3C_X500S,
+ };
+ 
+ static const struct hda_fixup alc662_fixups[] = {
+@@ -11248,6 +11249,13 @@ static const struct hda_fixup alc662_fixups[] = {
+               .chained = true,
+               .chain_id = ALC897_FIXUP_LENOVO_HEADSET_MODE
+       },
++      [ALC897_FIXUP_UNIS_H3C_X500S] = {
++              .type = HDA_FIXUP_VERBS,
++              .v.verbs = (const struct hda_verb[]) {
++                      { 0x14, AC_VERB_SET_EAPD_BTLENABLE, 0 },
++                      {}
++              },
++      },
+ };
+ 
+ static const struct snd_pci_quirk alc662_fixup_tbl[] = {
+@@ -11409,6 +11417,7 @@ static const struct hda_model_fixup alc662_fixup_models[] = {
+       {.id = ALC662_FIXUP_USI_HEADSET_MODE, .name = "usi-headset"},
+       {.id = ALC662_FIXUP_LENOVO_MULTI_CODECS, .name = "dual-codecs"},
+       {.id = ALC669_FIXUP_ACER_ASPIRE_ETHOS, .name = "aspire-ethos"},
++      {.id = ALC897_FIXUP_UNIS_H3C_X500S, .name = "unis-h3c-x500s"},
+       {}
+ };
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch b/queue-5.15/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
new file mode 100644 (file)
index 0000000..6cc2f73
--- /dev/null
+++ b/queue-5.15/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
@@ -0,0 +1,78 @@
+From cd977c31a043251b9fe334afe2a2ab102689f5a0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 27 Jan 2023 20:12:19 +0000
+Subject: apparmor: fix use of strcpy in policy_unpack_test
+
+From: Rae Moar <rmoar@google.com>
+
+[ Upstream commit b54aebd4411134b525a82d663a26b2f135ecb7e8 ]
+
+Replace the use of strcpy() in build_aa_ext_struct() in
+policy_unpack_test.c with strscpy().
+
+strscpy() is the safer method to use to ensure the buffer does not
+overflow. This was found by kernel test robot:
+https://lore.kernel.org/all/202301040348.NbfVsXO0-lkp@intel.com/.
+
+Reported-by: kernel test robot <lkp@intel.com>
+
+Signed-off-by: Rae Moar <rmoar@google.com>
+Signed-off-by: John Johansen <john.johansen@canonical.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ security/apparmor/policy_unpack_test.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/security/apparmor/policy_unpack_test.c b/security/apparmor/policy_unpack_test.c
+index 533137f45361c..3c84981aa1f48 100644
+--- a/security/apparmor/policy_unpack_test.c
++++ b/security/apparmor/policy_unpack_test.c
+@@ -66,31 +66,30 @@ struct aa_ext *build_aa_ext_struct(struct policy_unpack_fixture *puf,
+ 
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_STRING_NAME) + 1;
+-      strcpy(buf + 3, TEST_STRING_NAME);
++      strscpy(buf + 3, TEST_STRING_NAME, e->end - (void *)(buf + 3));
+ 
+       buf = e->start + TEST_STRING_BUF_OFFSET;
+       *buf = AA_STRING;
+       *(buf + 1) = strlen(TEST_STRING_DATA) + 1;
+-      strcpy(buf + 3, TEST_STRING_DATA);
+-
++      strscpy(buf + 3, TEST_STRING_DATA, e->end - (void *)(buf + 3));
+       buf = e->start + TEST_NAMED_U32_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_U32_NAME) + 1;
+-      strcpy(buf + 3, TEST_U32_NAME);
++      strscpy(buf + 3, TEST_U32_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_U32_NAME) + 1) = AA_U32;
+       *((u32 *)(buf + 3 + strlen(TEST_U32_NAME) + 2)) = TEST_U32_DATA;
+ 
+       buf = e->start + TEST_NAMED_U64_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_U64_NAME) + 1;
+-      strcpy(buf + 3, TEST_U64_NAME);
++      strscpy(buf + 3, TEST_U64_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_U64_NAME) + 1) = AA_U64;
+       *((u64 *)(buf + 3 + strlen(TEST_U64_NAME) + 2)) = TEST_U64_DATA;
+ 
+       buf = e->start + TEST_NAMED_BLOB_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_BLOB_NAME) + 1;
+-      strcpy(buf + 3, TEST_BLOB_NAME);
++      strscpy(buf + 3, TEST_BLOB_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_BLOB_NAME) + 1) = AA_BLOB;
+       *(buf + 3 + strlen(TEST_BLOB_NAME) + 2) = TEST_BLOB_DATA_SIZE;
+       memcpy(buf + 3 + strlen(TEST_BLOB_NAME) + 6,
+@@ -99,7 +98,7 @@ struct aa_ext *build_aa_ext_struct(struct policy_unpack_fixture *puf,
+       buf = e->start + TEST_NAMED_ARRAY_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_ARRAY_NAME) + 1;
+-      strcpy(buf + 3, TEST_ARRAY_NAME);
++      strscpy(buf + 3, TEST_ARRAY_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_ARRAY_NAME) + 1) = AA_ARRAY;
+       *((u16 *)(buf + 3 + strlen(TEST_ARRAY_NAME) + 2)) = TEST_ARRAY_SIZE;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/arm-dts-aspeed-asrock-correct-firmware-flash-spi-clo.patch b/queue-5.15/arm-dts-aspeed-asrock-correct-firmware-flash-spi-clo.patch
new file mode 100644 (file)
index 0000000..561cfb8
--- /dev/null
+++ b/queue-5.15/arm-dts-aspeed-asrock-correct-firmware-flash-spi-clo.patch
@@ -0,0 +1,40 @@
+From 209ccd867793e78c4ee408be2a76eee3fa1af627 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 23 Feb 2023 16:04:00 -0800
+Subject: ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks
+
+From: Zev Weiss <zev@bewilderbeest.net>
+
+[ Upstream commit 9dedb724446913ea7b1591b4b3d2e3e909090980 ]
+
+While I'm not aware of any problems that have occurred running these
+at 100 MHz, the official word from ASRock is that 50 MHz is the
+correct speed to use, so let's be safe and use that instead.
+
+Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
+Cc: stable@vger.kernel.org
+Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
+Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
+Link: https://lore.kernel.org/r/20230224000400.12226-4-zev@bewilderbeest.net
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+index 9b4cf5ebe6d5f..c62aff908ab48 100644
+--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
++++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+@@ -63,7 +63,7 @@ flash@0 {
+               status = "okay";
+               m25p,fast-read;
+               label = "bmc";
+-              spi-max-frequency = <100000000>; /* 100 MHz */
++              spi-max-frequency = <50000000>; /* 50 MHz */
+ #include "openbmc-flash-layout.dtsi"
+       };
+ };
+-- 
+2.40.1
+

diff --git a/queue-5.15/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch b/queue-5.15/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
new file mode 100644 (file)
index 0000000..bafe0b6
--- /dev/null
+++ b/queue-5.15/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
@@ -0,0 +1,79 @@
+From e96797feaa8ae7476f69652197ad863f68b820d3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 14:03:44 +0200
+Subject: ARM: dts: imx6dl: prtrvt, prtvt7, prti6q, prtwd2: fix USB related
+ warnings
+
+From: Oleksij Rempel <o.rempel@pengutronix.de>
+
+[ Upstream commit 1d14bd943fa2bbdfda1efbcc080b298fed5f1803 ]
+
+Fix USB-related warnings in prtrvt, prtvt7, prti6q and prtwd2 device trees
+by disabling unused usbphynop1 and usbphynop2 USB PHYs and providing proper
+configuration for the over-current detection. This fixes the following
+warnings with the current kernel:
+ usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests
+ usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests
+ imx_usb 2184200.usb: No over current polarity defined
+
+By the way, fix over-current detection on usbotg port for prtvt7, prti6q
+and prtwd2 boards. Only prtrvt do not have OC on USB OTG port.
+
+Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6dl-prtrvt.dts   |  4 ++++
+ arch/arm/boot/dts/imx6qdl-prti6q.dtsi | 11 ++++++++++-
+ 2 files changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts
+index 5ac84445e9cc1..90e01de8c2c15 100644
+--- a/arch/arm/boot/dts/imx6dl-prtrvt.dts
++++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts
+@@ -126,6 +126,10 @@ &usbh1 {
+       status = "disabled";
+ };
+ 
++&usbotg {
++      disable-over-current;
++};
++
+ &vpu {
+       status = "disabled";
+ };
+diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
+index 19578f660b092..70dfa07a16981 100644
+--- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
+@@ -69,6 +69,7 @@ &usbh1 {
+       vbus-supply = <&reg_usb_h1_vbus>;
+       phy_type = "utmi";
+       dr_mode = "host";
++      disable-over-current;
+       status = "okay";
+ };
+ 
+@@ -78,10 +79,18 @@ &usbotg {
+       pinctrl-0 = <&pinctrl_usbotg>;
+       phy_type = "utmi";
+       dr_mode = "host";
+-      disable-over-current;
++      over-current-active-low;
+       status = "okay";
+ };
+ 
++&usbphynop1 {
++      status = "disabled";
++};
++
++&usbphynop2 {
++      status = "disabled";
++};
++
+ &usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+-- 
+2.40.1
+

diff --git a/queue-5.15/arm-dts-imx6sll-fixup-of-operating-points.patch b/queue-5.15/arm-dts-imx6sll-fixup-of-operating-points.patch
new file mode 100644 (file)
index 0000000..2dc9fe9
--- /dev/null
+++ b/queue-5.15/arm-dts-imx6sll-fixup-of-operating-points.patch
@@ -0,0 +1,59 @@
+From 7c29103988c3574758f8dcf952b0570510983ffc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 24 Sep 2021 11:14:37 +0200
+Subject: ARM: dts: imx6sll: fixup of operating points
+
+From: Andreas Kemnade <andreas@kemnade.info>
+
+[ Upstream commit 1875903019ea6e32e6e544c1631b119e4fd60b20 ]
+
+Make operating point definitions comply with binding
+specifications.
+
+Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6sll.dtsi | 22 ++++++++++------------
+ 1 file changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
+index eecb2f68a1c32..2873369a57c02 100644
+--- a/arch/arm/boot/dts/imx6sll.dtsi
++++ b/arch/arm/boot/dts/imx6sll.dtsi
+@@ -51,20 +51,18 @@ cpu0: cpu@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+-                      operating-points = <
++                      operating-points =
+                               /* kHz    uV */
+-                              996000  1275000
+-                              792000  1175000
+-                              396000  1075000
+-                              198000  975000
+-                      >;
+-                      fsl,soc-operating-points = <
++                              <996000  1275000>,
++                              <792000  1175000>,
++                              <396000  1075000>,
++                              <198000   975000>;
++                      fsl,soc-operating-points =
+                               /* ARM kHz      SOC-PU uV */
+-                              996000          1175000
+-                              792000          1175000
+-                              396000          1175000
+-                              198000          1175000
+-                      >;
++                              <996000         1175000>,
++                              <792000         1175000>,
++                              <396000         1175000>,
++                              <198000         1175000>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
+                       clocks = <&clks IMX6SLL_CLK_ARM>,
+-- 
+2.40.1
+

diff --git a/queue-5.15/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch b/queue-5.15/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch
new file mode 100644 (file)
index 0000000..bb2d0d4
--- /dev/null
+++ b/queue-5.15/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch
@@ -0,0 +1,36 @@
+From 1555016d8221728b7881a26f325cef392a8c0d51 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Jul 2023 10:28:33 +0800
+Subject: ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node
+
+From: Xu Yang <xu.yang_2@nxp.com>
+
+[ Upstream commit ee70b908f77a9d8f689dea986f09e6d7dc481934 ]
+
+Property name "phy-3p0-supply" is used instead of "phy-reg_3p0-supply".
+
+Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll")
+cc: <stable@vger.kernel.org>
+Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6sll.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
+index 2873369a57c02..3659fd5ecfa62 100644
+--- a/arch/arm/boot/dts/imx6sll.dtsi
++++ b/arch/arm/boot/dts/imx6sll.dtsi
+@@ -552,7 +552,7 @@ usbphy2: usb-phy@20ca000 {
+                               reg = <0x020ca000 0x1000>;
+                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6SLL_CLK_USBPHY2>;
+-                              phy-reg_3p0-supply = <&reg_3p0>;
++                              phy-3p0-supply = <&reg_3p0>;
+                               fsl,anatop = <&anatop>;
+                       };
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/asoc-sof-intel-fix-soundwire-hdaudio-mutual-exclusio.patch b/queue-5.15/asoc-sof-intel-fix-soundwire-hdaudio-mutual-exclusio.patch
new file mode 100644 (file)
index 0000000..553b3c3
--- /dev/null
+++ b/queue-5.15/asoc-sof-intel-fix-soundwire-hdaudio-mutual-exclusio.patch
@@ -0,0 +1,61 @@
+From 6a25475b3bff45bd3368f4ed52eceb7d163b9b8b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Jun 2023 17:25:28 -0500
+Subject: ASoC: SOF: Intel: fix SoundWire/HDaudio mutual exclusion
+
+From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+
+[ Upstream commit f751b99255cacd9ffe8c4bbf99767ad670cee1f7 ]
+
+The functionality described in Commit 61bef9e68dca ("ASoC: SOF: Intel: hda: enforce exclusion between HDaudio and SoundWire")
+does not seem to be properly implemented with two issues that need to
+be corrected.
+
+a) The test used is incorrect when DisplayAudio codecs are not supported.
+
+b) Conversely when only Display Audio codecs can be found, we do want
+to start the SoundWire links, if any. That will help add the relevant
+topologies and machine descriptors, and identify cases where the
+SoundWire information in ACPI needs to be modified with a quirk.
+
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+Link: https://lore.kernel.org/r/20230606222529.57156-2-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/sof/intel/hda.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
+index 35cbef171f4a3..038d09f6203aa 100644
+--- a/sound/soc/sof/intel/hda.c
++++ b/sound/soc/sof/intel/hda.c
+@@ -1040,12 +1040,22 @@ static int hda_generic_machine_select(struct snd_sof_dev *sdev)
+                       pdata->machine = hda_mach;
+                       pdata->tplg_filename = tplg_filename;
+ 
+-                      if (codec_num == 2) {
++                      if (codec_num == 2 ||
++                          (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) {
+                               /*
+                                * Prevent SoundWire links from starting when an external
+                                * HDaudio codec is used
+                                */
+                               hda_mach->mach_params.link_mask = 0;
++                      } else {
++                              /*
++                               * Allow SoundWire links to start when no external HDaudio codec
++                               * was detected. This will not create a SoundWire card but
++                               * will help detect if any SoundWire codec reports as ATTACHED.
++                               */
++                              struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
++
++                              hda_mach->mach_params.link_mask = hdev->info.link_mask;
+                       }
+               }
+       }
+-- 
+2.40.1
+

diff --git a/queue-5.15/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch b/queue-5.15/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
new file mode 100644 (file)
index 0000000..a74eeac
--- /dev/null
+++ b/queue-5.15/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
@@ -0,0 +1,37 @@
+From 081beed148ab0340287483e9fa71b81b777f2f20 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Jun 2023 12:08:10 -0500
+Subject: Bluetooth: btusb: Add MT7922 bluetooth ID for the Asus Ally
+
+From: Matthew Anderson <ruinairas1992@gmail.com>
+
+[ Upstream commit fa01eba11f0e57c767a5eab5291c7a01407a00be ]
+
+Adding the device ID from the Asus Ally gets the bluetooth working
+on the device.
+
+Signed-off-by: Matthew Anderson <ruinairas1992@gmail.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bluetooth/btusb.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
+index 9eb2267bd3a02..15d253325fd8a 100644
+--- a/drivers/bluetooth/btusb.c
++++ b/drivers/bluetooth/btusb.c
+@@ -475,6 +475,9 @@ static const struct usb_device_id blacklist_table[] = {
+       { USB_DEVICE(0x0489, 0xe0d9), .driver_info = BTUSB_MEDIATEK |
+                                                    BTUSB_WIDEBAND_SPEECH |
+                                                    BTUSB_VALID_LE_STATES },
++      { USB_DEVICE(0x0489, 0xe0f5), .driver_info = BTUSB_MEDIATEK |
++                                                   BTUSB_WIDEBAND_SPEECH |
++                                                   BTUSB_VALID_LE_STATES },
+       { USB_DEVICE(0x13d3, 0x3568), .driver_info = BTUSB_MEDIATEK |
+                                                    BTUSB_WIDEBAND_SPEECH |
+                                                    BTUSB_VALID_LE_STATES },
+-- 
+2.40.1
+

diff --git a/queue-5.15/bluetooth-l2cap-fix-use-after-free.patch b/queue-5.15/bluetooth-l2cap-fix-use-after-free.patch
new file mode 100644 (file)
index 0000000..2a8ab9e
--- /dev/null
+++ b/queue-5.15/bluetooth-l2cap-fix-use-after-free.patch
@@ -0,0 +1,41 @@
+From bc50c8342ae76f3f94b9d671cc480e95b70caecb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 May 2023 17:04:15 -0700
+Subject: Bluetooth: L2CAP: Fix use-after-free
+
+From: Zhengping Jiang <jiangzp@google.com>
+
+[ Upstream commit f752a0b334bb95fe9b42ecb511e0864e2768046f ]
+
+Fix potential use-after-free in l2cap_le_command_rej.
+
+Signed-off-by: Zhengping Jiang <jiangzp@google.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/l2cap_core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
+index 9dd54247029a8..0770286ecf0bc 100644
+--- a/net/bluetooth/l2cap_core.c
++++ b/net/bluetooth/l2cap_core.c
+@@ -6375,9 +6375,14 @@ static inline int l2cap_le_command_rej(struct l2cap_conn *conn,
+       if (!chan)
+               goto done;
+ 
++      chan = l2cap_chan_hold_unless_zero(chan);
++      if (!chan)
++              goto done;
++
+       l2cap_chan_lock(chan);
+       l2cap_chan_del(chan, ECONNREFUSED);
+       l2cap_chan_unlock(chan);
++      l2cap_chan_put(chan);
+ 
+ done:
+       mutex_unlock(&conn->chan_lock);
+-- 
+2.40.1
+

diff --git a/queue-5.15/btrfs-move-out-now-unused-bg-from-the-reclaim-list.patch b/queue-5.15/btrfs-move-out-now-unused-bg-from-the-reclaim-list.patch
new file mode 100644 (file)
index 0000000..ccaa0ba
--- /dev/null
+++ b/queue-5.15/btrfs-move-out-now-unused-bg-from-the-reclaim-list.patch
@@ -0,0 +1,52 @@
+From d822ad0705cb53beec76fbb1c67670088f9199b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Jun 2023 14:36:34 +0900
+Subject: btrfs: move out now unused BG from the reclaim list
+
+From: Naohiro Aota <naota@elisp.net>
+
+[ Upstream commit a9f189716cf15913c453299d72f69c51a9b0f86b ]
+
+An unused block group is easy to remove to free up space and should be
+reclaimed fast. Such block group can often already be a target of the
+reclaim process. As we check list_empty(&bg->bg_list), we keep it in the
+reclaim list. That block group is never reclaimed until the file system
+is filled e.g. up to 75%.
+
+Instead, we can move unused block group to the unused list and delete it
+fast.
+
+Fixes: 18bb8bbf13c1 ("btrfs: zoned: automatically reclaim zones")
+CC: stable@vger.kernel.org # 5.15+
+Reviewed-by: Filipe Manana <fdmanana@suse.com>
+Reviewed-by: Johannes Thumshirn <johannes.thumshirn@wdc.com>
+Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/block-group.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c
+index d24cef671c1aa..4ca6828586af5 100644
+--- a/fs/btrfs/block-group.c
++++ b/fs/btrfs/block-group.c
+@@ -1475,11 +1475,14 @@ void btrfs_mark_bg_unused(struct btrfs_block_group *bg)
+ {
+       struct btrfs_fs_info *fs_info = bg->fs_info;
+ 
++      trace_btrfs_add_unused_block_group(bg);
+       spin_lock(&fs_info->unused_bgs_lock);
+       if (list_empty(&bg->bg_list)) {
+               btrfs_get_block_group(bg);
+-              trace_btrfs_add_unused_block_group(bg);
+               list_add_tail(&bg->bg_list, &fs_info->unused_bgs);
++      } else {
++              /* Pull out the block group from the reclaim_bgs list. */
++              list_move_tail(&bg->bg_list, &fs_info->unused_bgs);
+       }
+       spin_unlock(&fs_info->unused_bgs_lock);
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/can-raw-fix-lockdep-issue-in-raw_release.patch b/queue-5.15/can-raw-fix-lockdep-issue-in-raw_release.patch
new file mode 100644 (file)
index 0000000..23d23eb
--- /dev/null
+++ b/queue-5.15/can-raw-fix-lockdep-issue-in-raw_release.patch
@@ -0,0 +1,159 @@
+From 59958781417319b55ca679bedf951efb6cf1d8d7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 20 Jul 2023 11:44:38 +0000
+Subject: can: raw: fix lockdep issue in raw_release()
+
+From: Eric Dumazet <edumazet@google.com>
+
+[ Upstream commit 11c9027c983e9e4b408ee5613b6504d24ebd85be ]
+
+syzbot complained about a lockdep issue [1]
+
+Since raw_bind() and raw_setsockopt() first get RTNL
+before locking the socket, we must adopt the same order in raw_release()
+
+[1]
+WARNING: possible circular locking dependency detected
+6.5.0-rc1-syzkaller-00192-g78adb4bcf99e #0 Not tainted
+------------------------------------------------------
+syz-executor.0/14110 is trying to acquire lock:
+ffff88804e4b6130 (sk_lock-AF_CAN){+.+.}-{0:0}, at: lock_sock include/net/sock.h:1708 [inline]
+ffff88804e4b6130 (sk_lock-AF_CAN){+.+.}-{0:0}, at: raw_bind+0xb1/0xab0 net/can/raw.c:435
+
+but task is already holding lock:
+ffffffff8e3df368 (rtnl_mutex){+.+.}-{3:3}, at: raw_bind+0xa7/0xab0 net/can/raw.c:434
+
+which lock already depends on the new lock.
+
+the existing dependency chain (in reverse order) is:
+
+-> #1 (rtnl_mutex){+.+.}-{3:3}:
+__mutex_lock_common kernel/locking/mutex.c:603 [inline]
+__mutex_lock+0x181/0x1340 kernel/locking/mutex.c:747
+raw_release+0x1c6/0x9b0 net/can/raw.c:391
+__sock_release+0xcd/0x290 net/socket.c:654
+sock_close+0x1c/0x20 net/socket.c:1386
+__fput+0x3fd/0xac0 fs/file_table.c:384
+task_work_run+0x14d/0x240 kernel/task_work.c:179
+resume_user_mode_work include/linux/resume_user_mode.h:49 [inline]
+exit_to_user_mode_loop kernel/entry/common.c:171 [inline]
+exit_to_user_mode_prepare+0x210/0x240 kernel/entry/common.c:204
+__syscall_exit_to_user_mode_work kernel/entry/common.c:286 [inline]
+syscall_exit_to_user_mode+0x1d/0x50 kernel/entry/common.c:297
+do_syscall_64+0x44/0xb0 arch/x86/entry/common.c:86
+entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+-> #0 (sk_lock-AF_CAN){+.+.}-{0:0}:
+check_prev_add kernel/locking/lockdep.c:3142 [inline]
+check_prevs_add kernel/locking/lockdep.c:3261 [inline]
+validate_chain kernel/locking/lockdep.c:3876 [inline]
+__lock_acquire+0x2e3d/0x5de0 kernel/locking/lockdep.c:5144
+lock_acquire kernel/locking/lockdep.c:5761 [inline]
+lock_acquire+0x1ae/0x510 kernel/locking/lockdep.c:5726
+lock_sock_nested+0x3a/0xf0 net/core/sock.c:3492
+lock_sock include/net/sock.h:1708 [inline]
+raw_bind+0xb1/0xab0 net/can/raw.c:435
+__sys_bind+0x1ec/0x220 net/socket.c:1792
+__do_sys_bind net/socket.c:1803 [inline]
+__se_sys_bind net/socket.c:1801 [inline]
+__x64_sys_bind+0x72/0xb0 net/socket.c:1801
+do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80
+entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+other info that might help us debug this:
+
+Possible unsafe locking scenario:
+
+CPU0 CPU1
+---- ----
+lock(rtnl_mutex);
+        lock(sk_lock-AF_CAN);
+        lock(rtnl_mutex);
+lock(sk_lock-AF_CAN);
+
+*** DEADLOCK ***
+
+1 lock held by syz-executor.0/14110:
+
+stack backtrace:
+CPU: 0 PID: 14110 Comm: syz-executor.0 Not tainted 6.5.0-rc1-syzkaller-00192-g78adb4bcf99e #0
+Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/03/2023
+Call Trace:
+<TASK>
+__dump_stack lib/dump_stack.c:88 [inline]
+dump_stack_lvl+0xd9/0x1b0 lib/dump_stack.c:106
+check_noncircular+0x311/0x3f0 kernel/locking/lockdep.c:2195
+check_prev_add kernel/locking/lockdep.c:3142 [inline]
+check_prevs_add kernel/locking/lockdep.c:3261 [inline]
+validate_chain kernel/locking/lockdep.c:3876 [inline]
+__lock_acquire+0x2e3d/0x5de0 kernel/locking/lockdep.c:5144
+lock_acquire kernel/locking/lockdep.c:5761 [inline]
+lock_acquire+0x1ae/0x510 kernel/locking/lockdep.c:5726
+lock_sock_nested+0x3a/0xf0 net/core/sock.c:3492
+lock_sock include/net/sock.h:1708 [inline]
+raw_bind+0xb1/0xab0 net/can/raw.c:435
+__sys_bind+0x1ec/0x220 net/socket.c:1792
+__do_sys_bind net/socket.c:1803 [inline]
+__se_sys_bind net/socket.c:1801 [inline]
+__x64_sys_bind+0x72/0xb0 net/socket.c:1801
+do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80
+entry_SYSCALL_64_after_hwframe+0x63/0xcd
+RIP: 0033:0x7fd89007cb29
+Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 e1 20 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b0 ff ff ff f7 d8 64 89 01 48
+RSP: 002b:00007fd890d2a0c8 EFLAGS: 00000246 ORIG_RAX: 0000000000000031
+RAX: ffffffffffffffda RBX: 00007fd89019bf80 RCX: 00007fd89007cb29
+RDX: 0000000000000010 RSI: 0000000020000040 RDI: 0000000000000003
+RBP: 00007fd8900c847a R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
+R13: 000000000000000b R14: 00007fd89019bf80 R15: 00007ffebf8124f8
+</TASK>
+
+Fixes: ee8b94c8510c ("can: raw: fix receiver memory leak")
+Reported-by: syzbot <syzkaller@googlegroups.com>
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Cc: Ziyang Xuan <william.xuanziyang@huawei.com>
+Cc: Oliver Hartkopp <socketcan@hartkopp.net>
+Cc: stable@vger.kernel.org
+Cc: Marc Kleine-Budde <mkl@pengutronix.de>
+Link: https://lore.kernel.org/all/20230720114438.172434-1-edumazet@google.com
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/can/raw.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/net/can/raw.c b/net/can/raw.c
+index afa76ce0bf608..c02df37894ff9 100644
+--- a/net/can/raw.c
++++ b/net/can/raw.c
+@@ -383,9 +383,9 @@ static int raw_release(struct socket *sock)
+       list_del(&ro->notifier);
+       spin_unlock(&raw_notifier_lock);
+ 
++      rtnl_lock();
+       lock_sock(sk);
+ 
+-      rtnl_lock();
+       /* remove current filters & unregister */
+       if (ro->bound) {
+               if (ro->dev)
+@@ -402,12 +402,13 @@ static int raw_release(struct socket *sock)
+       ro->dev = NULL;
+       ro->count = 0;
+       free_percpu(ro->uniq);
+-      rtnl_unlock();
+ 
+       sock_orphan(sk);
+       sock->sk = NULL;
+ 
+       release_sock(sk);
++      rtnl_unlock();
++
+       sock_put(sk);
+ 
+       return 0;
+-- 
+2.40.1
+

diff --git a/queue-5.15/can-raw-fix-receiver-memory-leak.patch b/queue-5.15/can-raw-fix-receiver-memory-leak.patch
new file mode 100644 (file)
index 0000000..103700b
--- /dev/null
+++ b/queue-5.15/can-raw-fix-receiver-memory-leak.patch
@@ -0,0 +1,238 @@
+From 3629c40d9d559912ba1e25950e4ae8763f899d89 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Jul 2023 09:17:37 +0800
+Subject: can: raw: fix receiver memory leak
+
+From: Ziyang Xuan <william.xuanziyang@huawei.com>
+
+[ Upstream commit ee8b94c8510ce64afe0b87ef548d23e00915fb10 ]
+
+Got kmemleak errors with the following ltp can_filter testcase:
+
+for ((i=1; i<=100; i++))
+do
+        ./can_filter &
+        sleep 0.1
+done
+
+==============================================================
+[<00000000db4a4943>] can_rx_register+0x147/0x360 [can]
+[<00000000a289549d>] raw_setsockopt+0x5ef/0x853 [can_raw]
+[<000000006d3d9ebd>] __sys_setsockopt+0x173/0x2c0
+[<00000000407dbfec>] __x64_sys_setsockopt+0x61/0x70
+[<00000000fd468496>] do_syscall_64+0x33/0x40
+[<00000000b7e47d51>] entry_SYSCALL_64_after_hwframe+0x61/0xc6
+
+It's a bug in the concurrent scenario of unregister_netdevice_many()
+and raw_release() as following:
+
+             cpu0                                        cpu1
+unregister_netdevice_many(can_dev)
+  unlist_netdevice(can_dev) // dev_get_by_index() return NULL after this
+  net_set_todo(can_dev)
+                                               raw_release(can_socket)
+                                                 dev = dev_get_by_index(, ro->ifindex); // dev == NULL
+                                                 if (dev) { // receivers in dev_rcv_lists not free because dev is NULL
+                                                   raw_disable_allfilters(, dev, );
+                                                   dev_put(dev);
+                                                 }
+                                                 ...
+                                                 ro->bound = 0;
+                                                 ...
+
+call_netdevice_notifiers(NETDEV_UNREGISTER, )
+  raw_notify(, NETDEV_UNREGISTER, )
+    if (ro->bound) // invalid because ro->bound has been set 0
+      raw_disable_allfilters(, dev, ); // receivers in dev_rcv_lists will never be freed
+
+Add a net_device pointer member in struct raw_sock to record bound
+can_dev, and use rtnl_lock to serialize raw_socket members between
+raw_bind(), raw_release(), raw_setsockopt() and raw_notify(). Use
+ro->dev to decide whether to free receivers in dev_rcv_lists.
+
+Fixes: 8d0caedb7596 ("can: bcm/raw/isotp: use per module netdevice notifier")
+Reviewed-by: Oliver Hartkopp <socketcan@hartkopp.net>
+Acked-by: Oliver Hartkopp <socketcan@hartkopp.net>
+Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com>
+Link: https://lore.kernel.org/all/20230711011737.1969582-1-william.xuanziyang@huawei.com
+Cc: stable@vger.kernel.org
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/can/raw.c | 57 ++++++++++++++++++++++-----------------------------
+ 1 file changed, 24 insertions(+), 33 deletions(-)
+
+diff --git a/net/can/raw.c b/net/can/raw.c
+index 7105fa4824e4b..afa76ce0bf608 100644
+--- a/net/can/raw.c
++++ b/net/can/raw.c
+@@ -83,6 +83,7 @@ struct raw_sock {
+       struct sock sk;
+       int bound;
+       int ifindex;
++      struct net_device *dev;
+       struct list_head notifier;
+       int loopback;
+       int recv_own_msgs;
+@@ -275,7 +276,7 @@ static void raw_notify(struct raw_sock *ro, unsigned long msg,
+       if (!net_eq(dev_net(dev), sock_net(sk)))
+               return;
+ 
+-      if (ro->ifindex != dev->ifindex)
++      if (ro->dev != dev)
+               return;
+ 
+       switch (msg) {
+@@ -290,6 +291,7 @@ static void raw_notify(struct raw_sock *ro, unsigned long msg,
+ 
+               ro->ifindex = 0;
+               ro->bound = 0;
++              ro->dev = NULL;
+               ro->count = 0;
+               release_sock(sk);
+ 
+@@ -335,6 +337,7 @@ static int raw_init(struct sock *sk)
+ 
+       ro->bound            = 0;
+       ro->ifindex          = 0;
++      ro->dev              = NULL;
+ 
+       /* set default filter to single entry dfilter */
+       ro->dfilter.can_id   = 0;
+@@ -382,19 +385,13 @@ static int raw_release(struct socket *sock)
+ 
+       lock_sock(sk);
+ 
++      rtnl_lock();
+       /* remove current filters & unregister */
+       if (ro->bound) {
+-              if (ro->ifindex) {
+-                      struct net_device *dev;
+-
+-                      dev = dev_get_by_index(sock_net(sk), ro->ifindex);
+-                      if (dev) {
+-                              raw_disable_allfilters(dev_net(dev), dev, sk);
+-                              dev_put(dev);
+-                      }
+-              } else {
++              if (ro->dev)
++                      raw_disable_allfilters(dev_net(ro->dev), ro->dev, sk);
++              else
+                       raw_disable_allfilters(sock_net(sk), NULL, sk);
+-              }
+       }
+ 
+       if (ro->count > 1)
+@@ -402,8 +399,10 @@ static int raw_release(struct socket *sock)
+ 
+       ro->ifindex = 0;
+       ro->bound = 0;
++      ro->dev = NULL;
+       ro->count = 0;
+       free_percpu(ro->uniq);
++      rtnl_unlock();
+ 
+       sock_orphan(sk);
+       sock->sk = NULL;
+@@ -419,6 +418,7 @@ static int raw_bind(struct socket *sock, struct sockaddr *uaddr, int len)
+       struct sockaddr_can *addr = (struct sockaddr_can *)uaddr;
+       struct sock *sk = sock->sk;
+       struct raw_sock *ro = raw_sk(sk);
++      struct net_device *dev = NULL;
+       int ifindex;
+       int err = 0;
+       int notify_enetdown = 0;
+@@ -428,14 +428,13 @@ static int raw_bind(struct socket *sock, struct sockaddr *uaddr, int len)
+       if (addr->can_family != AF_CAN)
+               return -EINVAL;
+ 
++      rtnl_lock();
+       lock_sock(sk);
+ 
+       if (ro->bound && addr->can_ifindex == ro->ifindex)
+               goto out;
+ 
+       if (addr->can_ifindex) {
+-              struct net_device *dev;
+-
+               dev = dev_get_by_index(sock_net(sk), addr->can_ifindex);
+               if (!dev) {
+                       err = -ENODEV;
+@@ -464,26 +463,20 @@ static int raw_bind(struct socket *sock, struct sockaddr *uaddr, int len)
+       if (!err) {
+               if (ro->bound) {
+                       /* unregister old filters */
+-                      if (ro->ifindex) {
+-                              struct net_device *dev;
+-
+-                              dev = dev_get_by_index(sock_net(sk),
+-                                                     ro->ifindex);
+-                              if (dev) {
+-                                      raw_disable_allfilters(dev_net(dev),
+-                                                             dev, sk);
+-                                      dev_put(dev);
+-                              }
+-                      } else {
++                      if (ro->dev)
++                              raw_disable_allfilters(dev_net(ro->dev),
++                                                     ro->dev, sk);
++                      else
+                               raw_disable_allfilters(sock_net(sk), NULL, sk);
+-                      }
+               }
+               ro->ifindex = ifindex;
+               ro->bound = 1;
++              ro->dev = dev;
+       }
+ 
+  out:
+       release_sock(sk);
++      rtnl_unlock();
+ 
+       if (notify_enetdown) {
+               sk->sk_err = ENETDOWN;
+@@ -549,9 +542,9 @@ static int raw_setsockopt(struct socket *sock, int level, int optname,
+               rtnl_lock();
+               lock_sock(sk);
+ 
+-              if (ro->bound && ro->ifindex) {
+-                      dev = dev_get_by_index(sock_net(sk), ro->ifindex);
+-                      if (!dev) {
++              dev = ro->dev;
++              if (ro->bound && dev) {
++                      if (dev->reg_state != NETREG_REGISTERED) {
+                               if (count > 1)
+                                       kfree(filter);
+                               err = -ENODEV;
+@@ -592,7 +585,6 @@ static int raw_setsockopt(struct socket *sock, int level, int optname,
+               ro->count  = count;
+ 
+  out_fil:
+-              dev_put(dev);
+               release_sock(sk);
+               rtnl_unlock();
+ 
+@@ -610,9 +602,9 @@ static int raw_setsockopt(struct socket *sock, int level, int optname,
+               rtnl_lock();
+               lock_sock(sk);
+ 
+-              if (ro->bound && ro->ifindex) {
+-                      dev = dev_get_by_index(sock_net(sk), ro->ifindex);
+-                      if (!dev) {
++              dev = ro->dev;
++              if (ro->bound && dev) {
++                      if (dev->reg_state != NETREG_REGISTERED) {
+                               err = -ENODEV;
+                               goto out_err;
+                       }
+@@ -636,7 +628,6 @@ static int raw_setsockopt(struct socket *sock, int level, int optname,
+               ro->err_mask = err_mask;
+ 
+  out_err:
+-              dev_put(dev);
+               release_sock(sk);
+               rtnl_unlock();
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch b/queue-5.15/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
new file mode 100644 (file)
index 0000000..ce4f2d1
--- /dev/null
+++ b/queue-5.15/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
@@ -0,0 +1,63 @@
+From fe2a378b9e173c3a9fc473d9be3ed09292a057b3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Jun 2023 12:47:37 +0000
+Subject: dma-remap: use kvmalloc_array/kvfree for larger dma memory remap
+
+From: gaoxu <gaoxu2@hihonor.com>
+
+[ Upstream commit 51ff97d54f02b4444dfc42e380ac4c058e12d5dd ]
+
+If dma_direct_alloc() alloc memory in size of 64MB, the inner function
+dma_common_contiguous_remap() will allocate 128KB memory by invoking
+the function kmalloc_array(). and the kmalloc_array seems to fail to try to
+allocate 128KB mem.
+
+Call trace:
+[14977.928623] qcrosvm: page allocation failure: order:5, mode:0x40cc0
+[14977.928638] dump_backtrace.cfi_jt+0x0/0x8
+[14977.928647] dump_stack_lvl+0x80/0xb8
+[14977.928652] warn_alloc+0x164/0x200
+[14977.928657] __alloc_pages_slowpath+0x9f0/0xb4c
+[14977.928660] __alloc_pages+0x21c/0x39c
+[14977.928662] kmalloc_order+0x48/0x108
+[14977.928666] kmalloc_order_trace+0x34/0x154
+[14977.928668] __kmalloc+0x548/0x7e4
+[14977.928673] dma_direct_alloc+0x11c/0x4f8
+[14977.928678] dma_alloc_attrs+0xf4/0x138
+[14977.928680] gh_vm_ioctl_set_fw_name+0x3c4/0x610 [gunyah]
+[14977.928698] gh_vm_ioctl+0x90/0x14c [gunyah]
+[14977.928705] __arm64_sys_ioctl+0x184/0x210
+
+work around by doing kvmalloc_array instead.
+
+Signed-off-by: Gao Xu <gaoxu2@hihonor.com>
+Reviewed-by: Suren Baghdasaryan <surenb@google.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/dma/remap.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/dma/remap.c b/kernel/dma/remap.c
+index b4526668072e7..27596f3b4aef3 100644
+--- a/kernel/dma/remap.c
++++ b/kernel/dma/remap.c
+@@ -43,13 +43,13 @@ void *dma_common_contiguous_remap(struct page *page, size_t size,
+       void *vaddr;
+       int i;
+ 
+-      pages = kmalloc_array(count, sizeof(struct page *), GFP_KERNEL);
++      pages = kvmalloc_array(count, sizeof(struct page *), GFP_KERNEL);
+       if (!pages)
+               return NULL;
+       for (i = 0; i < count; i++)
+               pages[i] = nth_page(page, i);
+       vaddr = vmap(pages, count, VM_DMA_COHERENT, prot);
+-      kfree(pages);
++      kvfree(pages);
+ 
+       return vaddr;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/drm-amd-display-fix-access-hdcp_workqueue-assert.patch b/queue-5.15/drm-amd-display-fix-access-hdcp_workqueue-assert.patch
new file mode 100644 (file)
index 0000000..05d10a7
--- /dev/null
+++ b/queue-5.15/drm-amd-display-fix-access-hdcp_workqueue-assert.patch
@@ -0,0 +1,81 @@
+From 0418be890039a4e8a98a6e8fe276ffb553106be4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Mar 2023 10:45:24 -0400
+Subject: drm/amd/display: fix access hdcp_workqueue assert
+
+From: Hersen Wu <hersenxs.wu@amd.com>
+
+[ Upstream commit cdff36a0217aadf5cbc167893ad1c0da869619cb ]
+
+[Why] hdcp are enabled for asics from raven. for old asics
+which hdcp are not enabled, hdcp_workqueue are null. some
+access to hdcp work queue are not guarded with pointer check.
+
+[How] add hdcp_workqueue pointer check before access workqueue.
+
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    |  6 ++++++
+ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c  | 16 ++++++++++------
+ 2 files changed, 16 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 65f9e7012f6c4..4cf33abfb7cca 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -9634,6 +9634,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+               struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+               struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 
++              if (!adev->dm.hdcp_workqueue)
++                      continue;
++
+               pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
+ 
+               if (!connector)
+@@ -9682,6 +9685,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+               struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+               struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 
++              if (!adev->dm.hdcp_workqueue)
++                      continue;
++
+               new_crtc_state = NULL;
+               old_crtc_state = NULL;
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index e1e0be6dd22ca..0b58a93864490 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -331,13 +331,17 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
+               if (aconnector->dc_sink && connector->state) {
+                       struct drm_device *dev = connector->dev;
+                       struct amdgpu_device *adev = drm_to_adev(dev);
+-                      struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
+-                      struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index];
+ 
+-                      connector->state->hdcp_content_type =
+-                      hdcp_w->hdcp_content_type[connector->index];
+-                      connector->state->content_protection =
+-                      hdcp_w->content_protection[connector->index];
++                      if (adev->dm.hdcp_workqueue) {
++                              struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
++                              struct hdcp_workqueue *hdcp_w =
++                                      &hdcp_work[aconnector->dc_link->link_index];
++
++                              connector->state->hdcp_content_type =
++                              hdcp_w->hdcp_content_type[connector->index];
++                              connector->state->content_protection =
++                              hdcp_w->content_protection[connector->index];
++                      }
+               }
+ #endif
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/drm-amd-display-phase3-mst-hdcp-for-multiple-display.patch b/queue-5.15/drm-amd-display-phase3-mst-hdcp-for-multiple-display.patch
new file mode 100644 (file)
index 0000000..07da153
--- /dev/null
+++ b/queue-5.15/drm-amd-display-phase3-mst-hdcp-for-multiple-display.patch
@@ -0,0 +1,310 @@
+From af6c9c55603de49db0911abfa75b62f41e7f9caa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 15 Nov 2022 14:20:56 -0500
+Subject: drm/amd/display: phase3 mst hdcp for multiple displays
+
+From: hersen wu <hersenxs.wu@amd.com>
+
+[ Upstream commit e8fd3eeb5e8711af39b00642da06474e52f4780c ]
+
+[Why]
+multiple display hdcp are enabled within event_property_validate,
+event_property_update by looping all displays on mst hub. when
+one of display on mst hub in unplugged or disabled, hdcp are
+disabled for all displays on mst hub within hdcp_reset_display
+by looping all displays of mst link. for displays still active,
+their encryption status are off. kernel driver will not run hdcp
+authentication again. therefore, hdcp are not enabled automatically.
+
+[How]
+within is_content_protection_different, check drm_crtc_state changes
+of all displays on mst hub, if need, triger hdcp_update_display to
+re-run hdcp authentication.
+
+Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: hersen wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: cdff36a0217a ("drm/amd/display: fix access hdcp_workqueue assert")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 183 ++++++++++++++----
+ 1 file changed, 141 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 41be9606726e9..65f9e7012f6c4 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -8566,27 +8566,55 @@ is_scaling_state_different(const struct dm_connector_state *dm_state,
+ }
+ 
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+-static bool is_content_protection_different(struct drm_connector_state *state,
+-                                          const struct drm_connector_state *old_state,
+-                                          const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
++static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
++                                          struct drm_crtc_state *old_crtc_state,
++                                          struct drm_connector_state *new_conn_state,
++                                          struct drm_connector_state *old_conn_state,
++                                          const struct drm_connector *connector,
++                                          struct hdcp_workqueue *hdcp_w)
+ {
+       struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+       struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
+ 
+-      /* Handle: Type0/1 change */
+-      if (old_state->hdcp_content_type != state->hdcp_content_type &&
+-          state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+-              state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++      pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
++              connector->index, connector->status, connector->dpms);
++      pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
++              old_conn_state->content_protection, new_conn_state->content_protection);
++
++      if (old_crtc_state)
++              pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
++              old_crtc_state->enable,
++              old_crtc_state->active,
++              old_crtc_state->mode_changed,
++              old_crtc_state->active_changed,
++              old_crtc_state->connectors_changed);
++
++      if (new_crtc_state)
++              pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
++              new_crtc_state->enable,
++              new_crtc_state->active,
++              new_crtc_state->mode_changed,
++              new_crtc_state->active_changed,
++              new_crtc_state->connectors_changed);
++
++      /* hdcp content type change */
++      if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
++          new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
++              new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++              pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
+               return true;
+       }
+ 
+-      /* CP is being re enabled, ignore this
+-       *
+-       * Handles:     ENABLED -> DESIRED
+-       */
+-      if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+-          state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+-              state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
++      /* CP is being re enabled, ignore this */
++      if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
++          new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++              if (new_crtc_state && new_crtc_state->mode_changed) {
++                      new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++                      pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
++                      return true;
++              };
++              new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
++              pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
+               return false;
+       }
+ 
+@@ -8594,9 +8622,9 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+        *
+        * Handles:     UNDESIRED -> ENABLED
+        */
+-      if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
+-          state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
+-              state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++      if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
++          new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
++              new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ 
+       /* Stream removed and re-enabled
+        *
+@@ -8606,10 +8634,12 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+        *
+        * Handles:     DESIRED -> DESIRED (Special case)
+        */
+-      if (!(old_state->crtc && old_state->crtc->enabled) &&
+-              state->crtc && state->crtc->enabled &&
++      if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
++              new_conn_state->crtc && new_conn_state->crtc->enabled &&
+               connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+               dm_con_state->update_hdcp = false;
++              pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
++                      __func__);
+               return true;
+       }
+ 
+@@ -8621,35 +8651,42 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+        *
+        * Handles:     DESIRED -> DESIRED (Special case)
+        */
+-      if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+-          connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
++      if (dm_con_state->update_hdcp &&
++      new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
++      connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
+               dm_con_state->update_hdcp = false;
++              pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
++                      __func__);
+               return true;
+       }
+ 
+-      /*
+-       * Handles:     UNDESIRED -> UNDESIRED
+-       *              DESIRED -> DESIRED
+-       *              ENABLED -> ENABLED
+-       */
+-      if (old_state->content_protection == state->content_protection)
++      if (old_conn_state->content_protection == new_conn_state->content_protection) {
++              if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++                      if (new_crtc_state && new_crtc_state->mode_changed) {
++                              pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
++                                      __func__);
++                              return true;
++                      };
++                      pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
++                              __func__);
++                      return false;
++              };
++
++              pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
+               return false;
++      }
+ 
+-      /*
+-       * Handles:     UNDESIRED -> DESIRED
+-       *              DESIRED -> UNDESIRED
+-       *              ENABLED -> UNDESIRED
+-       */
+-      if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
++      if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
++              pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
++                      __func__);
+               return true;
++      }
+ 
+-      /*
+-       * Handles:     DESIRED -> ENABLED
+-       */
++      pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
+       return false;
+ }
+-
+ #endif
++
+ static void remove_stream(struct amdgpu_device *adev,
+                         struct amdgpu_crtc *acrtc,
+                         struct dc_stream_state *stream)
+@@ -9592,15 +9629,66 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+               }
+       }
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
++      for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
++              struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
++              struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
++              struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++
++              pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
++
++              if (!connector)
++                      continue;
++
++              pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
++                      connector->index, connector->status, connector->dpms);
++              pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
++                      old_con_state->content_protection, new_con_state->content_protection);
++
++              if (aconnector->dc_sink) {
++                      if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
++                              aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
++                              pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
++                              aconnector->dc_sink->edid_caps.display_name);
++                      }
++              }
++
++              new_crtc_state = NULL;
++              old_crtc_state = NULL;
++
++              if (acrtc) {
++                      new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
++                      old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
++              }
++
++              if (old_crtc_state)
++                      pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
++                      old_crtc_state->enable,
++                      old_crtc_state->active,
++                      old_crtc_state->mode_changed,
++                      old_crtc_state->active_changed,
++                      old_crtc_state->connectors_changed);
++
++              if (new_crtc_state)
++                      pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
++                      new_crtc_state->enable,
++                      new_crtc_state->active,
++                      new_crtc_state->mode_changed,
++                      new_crtc_state->active_changed,
++                      new_crtc_state->connectors_changed);
++      }
++
+       for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+               struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
+               struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+               struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 
+               new_crtc_state = NULL;
++              old_crtc_state = NULL;
+ 
+-              if (acrtc)
++              if (acrtc) {
+                       new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
++                      old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
++              }
+ 
+               dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ 
+@@ -9612,7 +9700,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+                       continue;
+               }
+ 
+-              if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) {
++              if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
++                                                                                      old_con_state, connector, adev->dm.hdcp_workqueue)) {
+                       /* when display is unplugged from mst hub, connctor will
+                        * be destroyed within dm_dp_mst_connector_destroy. connector
+                        * hdcp perperties, like type, undesired, desired, enabled,
+@@ -9622,6 +9711,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+                        * will be retrieved from hdcp_work within dm_dp_mst_get_modes
+                        */
+ 
++                      bool enable_encryption = false;
++
++                      if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
++                              enable_encryption = true;
++
+                       if (aconnector->dc_link && aconnector->dc_sink &&
+                               aconnector->dc_link->type == dc_connection_mst_branch) {
+                               struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
+@@ -9634,11 +9728,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+                                       new_con_state->content_protection;
+                       }
+ 
++                      if (new_crtc_state && new_crtc_state->mode_changed &&
++                              new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
++                              enable_encryption = true;
++
++                      DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
++
+                       hdcp_update_display(
+                               adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
+-                              new_con_state->hdcp_content_type,
+-                              new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
+-    }
++                              new_con_state->hdcp_content_type, enable_encryption);
++              }
+       }
+ #endif
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/drm-amd-display-save-restore-hdcp-state-when-display.patch b/queue-5.15/drm-amd-display-save-restore-hdcp-state-when-display.patch
new file mode 100644 (file)
index 0000000..4ca2154
--- /dev/null
+++ b/queue-5.15/drm-amd-display-save-restore-hdcp-state-when-display.patch
@@ -0,0 +1,147 @@
+From 5e4c9e48ee6ff248ea3b30e593e2da34295316ca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 15 Nov 2022 10:39:55 -0500
+Subject: drm/amd/display: save restore hdcp state when display is unplugged
+ from mst hub
+
+From: hersen wu <hersenxs.wu@amd.com>
+
+[ Upstream commit 82986fd631fa04bcedaefe11a6b3767601cbe84f ]
+
+[Why]
+connector hdcp properties are lost after display is
+unplgged from mst hub. connector is destroyed with
+dm_dp_mst_connector_destroy. when display is plugged
+back, hdcp is not desired and it wouldnt be enabled.
+
+[How]
+save hdcp properties into hdcp_work within
+amdgpu_dm_atomic_commit_tail. If the same display is
+plugged back with same display index, its hdcp
+properties will be retrieved from hdcp_work within
+dm_dp_mst_get_modes.
+
+Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: hersen wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: cdff36a0217a ("drm/amd/display: fix access hdcp_workqueue assert")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 ++++++++++++++++-
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h    | 14 ++++++++++
+ .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 26 +++++++++++++++++++
+ 3 files changed, 63 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 7bd38d927b18c..41be9606726e9 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -9612,11 +9612,33 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+                       continue;
+               }
+ 
+-              if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
++              if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) {
++                      /* when display is unplugged from mst hub, connctor will
++                       * be destroyed within dm_dp_mst_connector_destroy. connector
++                       * hdcp perperties, like type, undesired, desired, enabled,
++                       * will be lost. So, save hdcp properties into hdcp_work within
++                       * amdgpu_dm_atomic_commit_tail. if the same display is
++                       * plugged back with same display index, its hdcp properties
++                       * will be retrieved from hdcp_work within dm_dp_mst_get_modes
++                       */
++
++                      if (aconnector->dc_link && aconnector->dc_sink &&
++                              aconnector->dc_link->type == dc_connection_mst_branch) {
++                              struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
++                              struct hdcp_workqueue *hdcp_w =
++                                      &hdcp_work[aconnector->dc_link->link_index];
++
++                              hdcp_w->hdcp_content_type[connector->index] =
++                                      new_con_state->hdcp_content_type;
++                              hdcp_w->content_protection[connector->index] =
++                                      new_con_state->content_protection;
++                      }
++
+                       hdcp_update_display(
+                               adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
+                               new_con_state->hdcp_content_type,
+                               new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
++    }
+       }
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index 09294ff122fea..bbbf7d0eff82f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -52,6 +52,20 @@ struct hdcp_workqueue {
+       struct mod_hdcp_link link;
+ 
+       enum mod_hdcp_encryption_status encryption_status;
++
++      /* when display is unplugged from mst hub, connctor will be
++       * destroyed within dm_dp_mst_connector_destroy. connector
++       * hdcp perperties, like type, undesired, desired, enabled,
++       * will be lost. So, save hdcp properties into hdcp_work within
++       * amdgpu_dm_atomic_commit_tail. if the same display is
++       * plugged back with same display index, its hdcp properties
++       * will be retrieved from hdcp_work within dm_dp_mst_get_modes
++       */
++      /* un-desired, desired, enabled */
++      unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX];
++      /* hdcp1.x, hdcp2.x */
++      unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX];
++
+       uint8_t max_link;
+ 
+       uint8_t *srm;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 7a3fee71a867a..e1e0be6dd22ca 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -32,6 +32,10 @@
+ #include "amdgpu_dm.h"
+ #include "amdgpu_dm_mst_types.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++#include "amdgpu_dm_hdcp.h"
++#endif
++
+ #include "dc.h"
+ #include "dm_helpers.h"
+ 
+@@ -315,6 +319,28 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
+               /* dc_link_add_remote_sink returns a new reference */
+               aconnector->dc_sink = dc_sink;
+ 
++              /* when display is unplugged from mst hub, connctor will be
++               * destroyed within dm_dp_mst_connector_destroy. connector
++               * hdcp perperties, like type, undesired, desired, enabled,
++               * will be lost. So, save hdcp properties into hdcp_work within
++               * amdgpu_dm_atomic_commit_tail. if the same display is
++               * plugged back with same display index, its hdcp properties
++               * will be retrieved from hdcp_work within dm_dp_mst_get_modes
++               */
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++              if (aconnector->dc_sink && connector->state) {
++                      struct drm_device *dev = connector->dev;
++                      struct amdgpu_device *adev = drm_to_adev(dev);
++                      struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
++                      struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index];
++
++                      connector->state->hdcp_content_type =
++                      hdcp_w->hdcp_content_type[connector->index];
++                      connector->state->content_protection =
++                      hdcp_w->content_protection[connector->index];
++              }
++#endif
++
+               if (aconnector->dc_sink) {
+                       amdgpu_dm_update_freesync_caps(
+                                       connector, aconnector->edid);
+-- 
+2.40.1
+

diff --git a/queue-5.15/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch b/queue-5.15/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
new file mode 100644 (file)
index 0000000..318e7ae
--- /dev/null
+++ b/queue-5.15/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
@@ -0,0 +1,52 @@
+From 3389b3479d3cfcdf7d7b5df86de580c29bda3fda Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Jun 2023 18:10:47 -0700
+Subject: drm/amdgpu: Fix potential fence use-after-free v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: shanzhulig <shanzhulig@gmail.com>
+
+[ Upstream commit 2e54154b9f27262efd0cb4f903cc7d5ad1fe9628 ]
+
+fence Decrements the reference count before exiting.
+Avoid Race Vulnerabilities for fence use-after-free.
+
+v2 (chk): actually fix the use after free and not just move it.
+
+Signed-off-by: shanzhulig <shanzhulig@gmail.com>
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 2fd4d8ad7e40d..4b01188385b28 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -1541,15 +1541,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
+                       continue;
+ 
+               r = dma_fence_wait_timeout(fence, true, timeout);
++              if (r > 0 && fence->error)
++                      r = fence->error;
++
+               dma_fence_put(fence);
+               if (r < 0)
+                       return r;
+ 
+               if (r == 0)
+                       break;
+-
+-              if (fence->error)
+-                      return fence->error;
+       }
+ 
+       memset(wait, 0, sizeof(*wait));
+-- 
+2.40.1
+

diff --git a/queue-5.15/drm-amdgpu-install-stub-fence-into-potential-unused-.patch b/queue-5.15/drm-amdgpu-install-stub-fence-into-potential-unused-.patch
new file mode 100644 (file)
index 0000000..13e662d
--- /dev/null
+++ b/queue-5.15/drm-amdgpu-install-stub-fence-into-potential-unused-.patch
@@ -0,0 +1,59 @@
+From f64e6d9190f76a8facfa91e30a3806c044f79850 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 5 May 2023 20:14:15 +0800
+Subject: drm/amdgpu: install stub fence into potential unused fence pointers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Lang Yu <Lang.Yu@amd.com>
+
+[ Upstream commit 187916e6ed9d0c3b3abc27429f7a5f8c936bd1f0 ]
+
+When using cpu to update page tables, vm update fences are unused.
+Install stub fence into these fence pointers instead of NULL
+to avoid NULL dereference when calling dma_fence_wait() on them.
+
+Suggested-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Lang Yu <Lang.Yu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 0e4554950e072..788611a50a68e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2260,6 +2260,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
+       amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
+ 
+       bo_va->ref_count = 1;
++      bo_va->last_pt_update = dma_fence_get_stub();
+       INIT_LIST_HEAD(&bo_va->valids);
+       INIT_LIST_HEAD(&bo_va->invalids);
+ 
+@@ -2974,7 +2975,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+               vm->update_funcs = &amdgpu_vm_cpu_funcs;
+       else
+               vm->update_funcs = &amdgpu_vm_sdma_funcs;
+-      vm->last_update = NULL;
++
++      vm->last_update = dma_fence_get_stub();
+       vm->last_unlocked = dma_fence_get_stub();
+ 
+       mutex_init(&vm->eviction_lock);
+@@ -3117,7 +3119,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+               vm->update_funcs = &amdgpu_vm_sdma_funcs;
+       }
+       dma_fence_put(vm->last_update);
+-      vm->last_update = NULL;
++      vm->last_update = dma_fence_get_stub();
+       vm->is_compute_context = true;
+ 
+       /* Free the shadow bo for compute VM */
+-- 
+2.40.1
+

diff --git a/queue-5.15/firewire-net-fix-use-after-free-in-fwnet_finish_inco.patch b/queue-5.15/firewire-net-fix-use-after-free-in-fwnet_finish_inco.patch
new file mode 100644 (file)
index 0000000..cad607e
--- /dev/null
+++ b/queue-5.15/firewire-net-fix-use-after-free-in-fwnet_finish_inco.patch
@@ -0,0 +1,53 @@
+From 14317b70b69607726db4dc505d6da31761a249da Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Jun 2023 13:39:35 +0800
+Subject: firewire: net: fix use after free in fwnet_finish_incoming_packet()
+
+From: Zhang Shurong <zhang_shurong@foxmail.com>
+
+[ Upstream commit 3ff256751a2853e1ffaa36958ff933ccc98c6cb5 ]
+
+The netif_rx() function frees the skb so we can't dereference it to
+save the skb->len.
+
+Signed-off-by: Zhang Shurong <zhang_shurong@foxmail.com>
+Link: https://lore.kernel.org/r/tencent_3B3D24B66ED66A6BB73CC0E63C6A14E45109@qq.com
+Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/firewire/net.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/firewire/net.c b/drivers/firewire/net.c
+index 4c3fd2eed1da4..beba0a56bb9ae 100644
+--- a/drivers/firewire/net.c
++++ b/drivers/firewire/net.c
+@@ -488,7 +488,7 @@ static int fwnet_finish_incoming_packet(struct net_device *net,
+                                       struct sk_buff *skb, u16 source_node_id,
+                                       bool is_broadcast, u16 ether_type)
+ {
+-      int status;
++      int status, len;
+ 
+       switch (ether_type) {
+       case ETH_P_ARP:
+@@ -542,13 +542,15 @@ static int fwnet_finish_incoming_packet(struct net_device *net,
+               }
+               skb->protocol = protocol;
+       }
++
++      len = skb->len;
+       status = netif_rx(skb);
+       if (status == NET_RX_DROP) {
+               net->stats.rx_errors++;
+               net->stats.rx_dropped++;
+       } else {
+               net->stats.rx_packets++;
+-              net->stats.rx_bytes += skb->len;
++              net->stats.rx_bytes += len;
+       }
+ 
+       return 0;
+-- 
+2.40.1
+

diff --git a/queue-5.15/fs-ntfs3-enhance-sanity-check-while-generating-attr_.patch b/queue-5.15/fs-ntfs3-enhance-sanity-check-while-generating-attr_.patch
new file mode 100644 (file)
index 0000000..238604b
--- /dev/null
+++ b/queue-5.15/fs-ntfs3-enhance-sanity-check-while-generating-attr_.patch
@@ -0,0 +1,199 @@
+From 35b4f68ebdbba120b5e0a3589065f3021bb15610 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Mar 2023 10:56:55 +0800
+Subject: fs/ntfs3: Enhance sanity check while generating attr_list
+
+From: Edward Lo <loyuantsung@gmail.com>
+
+[ Upstream commit fdec309c7672cbee4dc0229ee4cbb33c948a1bdd ]
+
+ni_create_attr_list uses WARN_ON to catch error cases while generating
+attribute list, which only prints out stack trace and may not be enough.
+This repalces them with more proper error handling flow.
+
+[   59.666332] BUG: kernel NULL pointer dereference, address: 000000000000000e
+[   59.673268] #PF: supervisor read access in kernel mode
+[   59.678354] #PF: error_code(0x0000) - not-present page
+[   59.682831] PGD 8000000005ff1067 P4D 8000000005ff1067 PUD 7dee067 PMD 0
+[   59.688556] Oops: 0000 [#1] PREEMPT SMP KASAN PTI
+[   59.692642] CPU: 0 PID: 198 Comm: poc Tainted: G    B   W          6.2.0-rc1+ #4
+[   59.698868] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014
+[   59.708795] RIP: 0010:ni_create_attr_list+0x505/0x860
+[   59.713657] Code: 7e 10 e8 5e d0 d0 ff 45 0f b7 76 10 48 8d 7b 16 e8 00 d1 d0 ff 66 44 89 73 16 4d 8d 75 0e 4c 89 f7 e8 3f d0 d0 ff 4c 8d8
+[   59.731559] RSP: 0018:ffff88800a56f1e0 EFLAGS: 00010282
+[   59.735691] RAX: 0000000000000001 RBX: ffff88800b7b5088 RCX: ffffffffb83079fe
+[   59.741792] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffffbb7f9fc0
+[   59.748423] RBP: ffff88800a56f3a8 R08: ffff88800b7b50a0 R09: fffffbfff76ff3f9
+[   59.754654] R10: ffffffffbb7f9fc7 R11: fffffbfff76ff3f8 R12: ffff88800b756180
+[   59.761552] R13: 0000000000000000 R14: 000000000000000e R15: 0000000000000050
+[   59.768323] FS:  00007feaa8c96440(0000) GS:ffff88806d400000(0000) knlGS:0000000000000000
+[   59.776027] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[   59.781395] CR2: 00007f3a2e0b1000 CR3: 000000000a5bc000 CR4: 00000000000006f0
+[   59.787607] Call Trace:
+[   59.790271]  <TASK>
+[   59.792488]  ? __pfx_ni_create_attr_list+0x10/0x10
+[   59.797235]  ? kernel_text_address+0xd3/0xe0
+[   59.800856]  ? unwind_get_return_address+0x3e/0x60
+[   59.805101]  ? __kasan_check_write+0x18/0x20
+[   59.809296]  ? preempt_count_sub+0x1c/0xd0
+[   59.813421]  ni_ins_attr_ext+0x52c/0x5c0
+[   59.817034]  ? __pfx_ni_ins_attr_ext+0x10/0x10
+[   59.821926]  ? __vfs_setxattr+0x121/0x170
+[   59.825718]  ? __vfs_setxattr_noperm+0x97/0x300
+[   59.829562]  ? __vfs_setxattr_locked+0x145/0x170
+[   59.833987]  ? vfs_setxattr+0x137/0x2a0
+[   59.836732]  ? do_setxattr+0xce/0x150
+[   59.839807]  ? setxattr+0x126/0x140
+[   59.842353]  ? path_setxattr+0x164/0x180
+[   59.845275]  ? __x64_sys_setxattr+0x71/0x90
+[   59.848838]  ? do_syscall_64+0x3f/0x90
+[   59.851898]  ? entry_SYSCALL_64_after_hwframe+0x72/0xdc
+[   59.857046]  ? stack_depot_save+0x17/0x20
+[   59.860299]  ni_insert_attr+0x1ba/0x420
+[   59.863104]  ? __pfx_ni_insert_attr+0x10/0x10
+[   59.867069]  ? preempt_count_sub+0x1c/0xd0
+[   59.869897]  ? _raw_spin_unlock_irqrestore+0x2b/0x50
+[   59.874088]  ? __create_object+0x3ae/0x5d0
+[   59.877865]  ni_insert_resident+0xc4/0x1c0
+[   59.881430]  ? __pfx_ni_insert_resident+0x10/0x10
+[   59.886355]  ? kasan_save_alloc_info+0x1f/0x30
+[   59.891117]  ? __kasan_kmalloc+0x8b/0xa0
+[   59.894383]  ntfs_set_ea+0x90d/0xbf0
+[   59.897703]  ? __pfx_ntfs_set_ea+0x10/0x10
+[   59.901011]  ? kernel_text_address+0xd3/0xe0
+[   59.905308]  ? __kernel_text_address+0x16/0x50
+[   59.909811]  ? unwind_get_return_address+0x3e/0x60
+[   59.914898]  ? __pfx_stack_trace_consume_entry+0x10/0x10
+[   59.920250]  ? arch_stack_walk+0xa2/0x100
+[   59.924560]  ? filter_irq_stacks+0x27/0x80
+[   59.928722]  ntfs_setxattr+0x405/0x440
+[   59.932512]  ? __pfx_ntfs_setxattr+0x10/0x10
+[   59.936634]  ? kvmalloc_node+0x2d/0x120
+[   59.940378]  ? kasan_save_stack+0x41/0x60
+[   59.943870]  ? kasan_save_stack+0x2a/0x60
+[   59.947719]  ? kasan_set_track+0x29/0x40
+[   59.951417]  ? kasan_save_alloc_info+0x1f/0x30
+[   59.955733]  ? __kasan_kmalloc+0x8b/0xa0
+[   59.959598]  ? __kmalloc_node+0x68/0x150
+[   59.963163]  ? kvmalloc_node+0x2d/0x120
+[   59.966490]  ? vmemdup_user+0x2b/0xa0
+[   59.969060]  __vfs_setxattr+0x121/0x170
+[   59.972456]  ? __pfx___vfs_setxattr+0x10/0x10
+[   59.976008]  __vfs_setxattr_noperm+0x97/0x300
+[   59.981562]  __vfs_setxattr_locked+0x145/0x170
+[   59.986100]  vfs_setxattr+0x137/0x2a0
+[   59.989964]  ? __pfx_vfs_setxattr+0x10/0x10
+[   59.993616]  ? __kasan_check_write+0x18/0x20
+[   59.997425]  do_setxattr+0xce/0x150
+[   60.000304]  setxattr+0x126/0x140
+[   60.002967]  ? __pfx_setxattr+0x10/0x10
+[   60.006471]  ? __virt_addr_valid+0xcb/0x140
+[   60.010461]  ? __call_rcu_common.constprop.0+0x1c7/0x330
+[   60.016037]  ? debug_smp_processor_id+0x1b/0x30
+[   60.021008]  ? kasan_quarantine_put+0x5b/0x190
+[   60.025545]  ? putname+0x84/0xa0
+[   60.027910]  ? __kasan_slab_free+0x11e/0x1b0
+[   60.031483]  ? putname+0x84/0xa0
+[   60.033986]  ? preempt_count_sub+0x1c/0xd0
+[   60.036876]  ? __mnt_want_write+0xae/0x100
+[   60.040738]  ? mnt_want_write+0x8f/0x150
+[   60.044317]  path_setxattr+0x164/0x180
+[   60.048096]  ? __pfx_path_setxattr+0x10/0x10
+[   60.052096]  ? strncpy_from_user+0x175/0x1c0
+[   60.056482]  ? debug_smp_processor_id+0x1b/0x30
+[   60.059848]  ? fpregs_assert_state_consistent+0x6b/0x80
+[   60.064557]  __x64_sys_setxattr+0x71/0x90
+[   60.068892]  do_syscall_64+0x3f/0x90
+[   60.072868]  entry_SYSCALL_64_after_hwframe+0x72/0xdc
+[   60.077523] RIP: 0033:0x7feaa86e4469
+[   60.080915] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 088
+[   60.097353] RSP: 002b:00007ffdbd8311e8 EFLAGS: 00000286 ORIG_RAX: 00000000000000bc
+[   60.103386] RAX: ffffffffffffffda RBX: 9461c5e290baac00 RCX: 00007feaa86e4469
+[   60.110322] RDX: 00007ffdbd831fe0 RSI: 00007ffdbd831305 RDI: 00007ffdbd831263
+[   60.116808] RBP: 00007ffdbd836180 R08: 0000000000000001 R09: 00007ffdbd836268
+[   60.123879] R10: 000000000000007d R11: 0000000000000286 R12: 0000000000400500
+[   60.130540] R13: 00007ffdbd836260 R14: 0000000000000000 R15: 0000000000000000
+[   60.136553]  </TASK>
+[   60.138818] Modules linked in:
+[   60.141839] CR2: 000000000000000e
+[   60.144831] ---[ end trace 0000000000000000 ]---
+[   60.149058] RIP: 0010:ni_create_attr_list+0x505/0x860
+[   60.153975] Code: 7e 10 e8 5e d0 d0 ff 45 0f b7 76 10 48 8d 7b 16 e8 00 d1 d0 ff 66 44 89 73 16 4d 8d 75 0e 4c 89 f7 e8 3f d0 d0 ff 4c 8d8
+[   60.172443] RSP: 0018:ffff88800a56f1e0 EFLAGS: 00010282
+[   60.176246] RAX: 0000000000000001 RBX: ffff88800b7b5088 RCX: ffffffffb83079fe
+[   60.182752] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffffbb7f9fc0
+[   60.189949] RBP: ffff88800a56f3a8 R08: ffff88800b7b50a0 R09: fffffbfff76ff3f9
+[   60.196950] R10: ffffffffbb7f9fc7 R11: fffffbfff76ff3f8 R12: ffff88800b756180
+[   60.203671] R13: 0000000000000000 R14: 000000000000000e R15: 0000000000000050
+[   60.209595] FS:  00007feaa8c96440(0000) GS:ffff88806d400000(0000) knlGS:0000000000000000
+[   60.216299] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[   60.222276] CR2: 00007f3a2e0b1000 CR3: 000000000a5bc000 CR4: 00000000000006f0
+
+Signed-off-by: Edward Lo <loyuantsung@gmail.com>
+Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ntfs3/frecord.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
+index d24e12d348d49..9a1744955d1cf 100644
+--- a/fs/ntfs3/frecord.c
++++ b/fs/ntfs3/frecord.c
+@@ -849,6 +849,7 @@ int ni_create_attr_list(struct ntfs_inode *ni)
+       if (err)
+               goto out1;
+ 
++      err = -EINVAL;
+       /* Call mi_remove_attr() in reverse order to keep pointers 'arr_move' valid. */
+       while (to_free > 0) {
+               struct ATTRIB *b = arr_move[--nb];
+@@ -857,7 +858,8 @@ int ni_create_attr_list(struct ntfs_inode *ni)
+ 
+               attr = mi_insert_attr(mi, b->type, Add2Ptr(b, name_off),
+                                     b->name_len, asize, name_off);
+-              WARN_ON(!attr);
++              if (!attr)
++                      goto out1;
+ 
+               mi_get_ref(mi, &le_b[nb]->ref);
+               le_b[nb]->id = attr->id;
+@@ -867,17 +869,20 @@ int ni_create_attr_list(struct ntfs_inode *ni)
+               attr->id = le_b[nb]->id;
+ 
+               /* Remove from primary record. */
+-              WARN_ON(!mi_remove_attr(NULL, &ni->mi, b));
++              if (!mi_remove_attr(NULL, &ni->mi, b))
++                      goto out1;
+ 
+               if (to_free <= asize)
+                       break;
+               to_free -= asize;
+-              WARN_ON(!nb);
++              if (!nb)
++                      goto out1;
+       }
+ 
+       attr = mi_insert_attr(&ni->mi, ATTR_LIST, NULL, 0,
+                             lsize + SIZEOF_RESIDENT, SIZEOF_RESIDENT);
+-      WARN_ON(!attr);
++      if (!attr)
++              goto out1;
+ 
+       attr->non_res = 0;
+       attr->flags = 0;
+@@ -897,9 +902,10 @@ int ni_create_attr_list(struct ntfs_inode *ni)
+       kfree(ni->attr_list.le);
+       ni->attr_list.le = NULL;
+       ni->attr_list.size = 0;
++      return err;
+ 
+ out:
+-      return err;
++      return 0;
+ }
+ 
+ /*
+-- 
+2.40.1
+

diff --git a/queue-5.15/fs-ntfs3-fix-possible-null-pointer-dereferences-in-m.patch b/queue-5.15/fs-ntfs3-fix-possible-null-pointer-dereferences-in-m.patch
new file mode 100644 (file)
index 0000000..df6e849
--- /dev/null
+++ b/queue-5.15/fs-ntfs3-fix-possible-null-pointer-dereferences-in-m.patch
@@ -0,0 +1,62 @@
+From 0c86e31bf6c009d11ef495c1d760e985fdf2972d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Mar 2023 21:22:11 +0800
+Subject: fs: ntfs3: Fix possible null-pointer dereferences in mi_read()
+
+From: Jia-Ju Bai <baijiaju@buaa.edu.cn>
+
+[ Upstream commit 97498cd610c0d030a7bd49a7efad974790661162 ]
+
+In a previous commit 2681631c2973 ("fs/ntfs3: Add null pointer check to
+attr_load_runs_vcn"), ni can be NULL in attr_load_runs_vcn(), and thus it
+should be checked before being used.
+
+However, in the call stack of this commit, mft_ni in mi_read() is
+aliased with ni in attr_load_runs_vcn(), and it is also used in
+mi_read() at two places:
+
+mi_read()
+  rw_lock = &mft_ni->file.run_lock -> No check
+  attr_load_runs_vcn(mft_ni, ...)
+    ni (namely mft_ni) is checked in the previous commit
+  attr_load_runs_vcn(..., &mft_ni->file.run) -> No check
+
+Thus, to avoid possible null-pointer dereferences, the related checks
+should be added.
+
+These bugs are reported by a static analysis tool implemented by myself,
+and they are found by extending a known bug fixed in the previous commit.
+Thus, they could be theoretical bugs.
+
+Signed-off-by: Jia-Ju Bai <baijiaju@buaa.edu.cn>
+Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ntfs3/record.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
+index 41f6e578966b2..3d222b1c8f038 100644
+--- a/fs/ntfs3/record.c
++++ b/fs/ntfs3/record.c
+@@ -124,7 +124,7 @@ int mi_read(struct mft_inode *mi, bool is_mft)
+       struct rw_semaphore *rw_lock = NULL;
+ 
+       if (is_mounted(sbi)) {
+-              if (!is_mft) {
++              if (!is_mft && mft_ni) {
+                       rw_lock = &mft_ni->file.run_lock;
+                       down_read(rw_lock);
+               }
+@@ -148,7 +148,7 @@ int mi_read(struct mft_inode *mi, bool is_mft)
+               ni_lock(mft_ni);
+               down_write(rw_lock);
+       }
+-      err = attr_load_runs_vcn(mft_ni, ATTR_DATA, NULL, 0, &mft_ni->file.run,
++      err = attr_load_runs_vcn(mft_ni, ATTR_DATA, NULL, 0, run,
+                                vbo >> sbi->cluster_bits);
+       if (rw_lock) {
+               up_write(rw_lock);
+-- 
+2.40.1
+

diff --git a/queue-5.15/fs-ntfs3-mark-ntfs-dirty-when-on-disk-struct-is-corr.patch b/queue-5.15/fs-ntfs3-mark-ntfs-dirty-when-on-disk-struct-is-corr.patch
new file mode 100644 (file)
index 0000000..a980556
--- /dev/null
+++ b/queue-5.15/fs-ntfs3-mark-ntfs-dirty-when-on-disk-struct-is-corr.patch
@@ -0,0 +1,81 @@
+From 532653cc3fe7d8fd1cd8ef32548c53e6b1f15298 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 May 2023 11:36:28 +0400
+Subject: fs/ntfs3: Mark ntfs dirty when on-disk struct is corrupted
+
+From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
+
+[ Upstream commit e0f363a98830e8d7d70fbaf91c07ae0b7c57aafe ]
+
+Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ntfs3/fsntfs.c  | 2 +-
+ fs/ntfs3/index.c   | 6 ++++++
+ fs/ntfs3/ntfs_fs.h | 2 ++
+ fs/ntfs3/record.c  | 6 ++++++
+ 4 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
+index 3c823613de97d..0ae70010b01d3 100644
+--- a/fs/ntfs3/fsntfs.c
++++ b/fs/ntfs3/fsntfs.c
+@@ -154,7 +154,7 @@ int ntfs_fix_post_read(struct NTFS_RECORD_HEADER *rhdr, size_t bytes,
+       /* Check errors. */
+       if ((fo & 1) || fo + fn * sizeof(short) > SECTOR_SIZE || !fn-- ||
+           fn * SECTOR_SIZE > bytes) {
+-              return -EINVAL; /* Native chkntfs returns ok! */
++              return -E_NTFS_CORRUPT;
+       }
+ 
+       /* Get fixup pointer. */
+diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
+index 124eba7238fd5..7705adc926b86 100644
+--- a/fs/ntfs3/index.c
++++ b/fs/ntfs3/index.c
+@@ -1112,6 +1112,12 @@ int indx_read(struct ntfs_index *indx, struct ntfs_inode *ni, CLST vbn,
+       *node = in;
+ 
+ out:
++      if (err == -E_NTFS_CORRUPT) {
++              ntfs_inode_err(&ni->vfs_inode, "directory corrupted");
++              ntfs_set_state(ni->mi.sbi, NTFS_DIRTY_ERROR);
++              err = -EINVAL;
++      }
++
+       if (ib != in->index)
+               kfree(ib);
+ 
+diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
+index fc0eb93c76de1..510ed2ea1c483 100644
+--- a/fs/ntfs3/ntfs_fs.h
++++ b/fs/ntfs3/ntfs_fs.h
+@@ -54,6 +54,8 @@ enum utf16_endian;
+ #define E_NTFS_NONRESIDENT            556
+ /* NTFS specific error code about punch hole. */
+ #define E_NTFS_NOTALIGNED             557
++/* NTFS specific error code when on-disk struct is corrupted. */
++#define E_NTFS_CORRUPT                        558
+ 
+ 
+ /* sbi->flags */
+diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
+index 3d222b1c8f038..938fc286963f2 100644
+--- a/fs/ntfs3/record.c
++++ b/fs/ntfs3/record.c
+@@ -180,6 +180,12 @@ int mi_read(struct mft_inode *mi, bool is_mft)
+       return 0;
+ 
+ out:
++      if (err == -E_NTFS_CORRUPT) {
++              ntfs_err(sbi->sb, "mft corrupted");
++              ntfs_set_state(sbi, NTFS_DIRTY_ERROR);
++              err = -EINVAL;
++      }
++
+       return err;
+ }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/gfs2-fix-possible-data-races-in-gfs2_show_options.patch b/queue-5.15/gfs2-fix-possible-data-races-in-gfs2_show_options.patch
new file mode 100644 (file)
index 0000000..e5f951f
--- /dev/null
+++ b/queue-5.15/gfs2-fix-possible-data-races-in-gfs2_show_options.patch
@@ -0,0 +1,86 @@
+From 203ee9b4464962b77e0d1851000bea296de74efd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Jun 2023 11:06:37 +0800
+Subject: gfs2: Fix possible data races in gfs2_show_options()
+
+From: Tuo Li <islituo@gmail.com>
+
+[ Upstream commit 6fa0a72cbbe45db4ed967a51f9e6f4e3afe61d20 ]
+
+Some fields such as gt_logd_secs of the struct gfs2_tune are accessed
+without holding the lock gt_spin in gfs2_show_options():
+
+  val = sdp->sd_tune.gt_logd_secs;
+  if (val != 30)
+    seq_printf(s, ",commit=%d", val);
+
+And thus can cause data races when gfs2_show_options() and other functions
+such as gfs2_reconfigure() are concurrently executed:
+
+  spin_lock(&gt->gt_spin);
+  gt->gt_logd_secs = newargs->ar_commit;
+
+To fix these possible data races, the lock sdp->sd_tune.gt_spin is
+acquired before accessing the fields of gfs2_tune and released after these
+accesses.
+
+Further changes by Andreas:
+
+- Don't hold the spin lock over the seq_printf operations.
+
+Reported-by: BassCheck <bass@buaa.edu.cn>
+Signed-off-by: Tuo Li <islituo@gmail.com>
+Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/gfs2/super.c | 26 +++++++++++++++-----------
+ 1 file changed, 15 insertions(+), 11 deletions(-)
+
+diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c
+index ca6ee1cbccd50..51b44da4a0d64 100644
+--- a/fs/gfs2/super.c
++++ b/fs/gfs2/super.c
+@@ -980,7 +980,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root)
+ {
+       struct gfs2_sbd *sdp = root->d_sb->s_fs_info;
+       struct gfs2_args *args = &sdp->sd_args;
+-      int val;
++      unsigned int logd_secs, statfs_slow, statfs_quantum, quota_quantum;
++
++      spin_lock(&sdp->sd_tune.gt_spin);
++      logd_secs = sdp->sd_tune.gt_logd_secs;
++      quota_quantum = sdp->sd_tune.gt_quota_quantum;
++      statfs_quantum = sdp->sd_tune.gt_statfs_quantum;
++      statfs_slow = sdp->sd_tune.gt_statfs_slow;
++      spin_unlock(&sdp->sd_tune.gt_spin);
+ 
+       if (is_ancestor(root, sdp->sd_master_dir))
+               seq_puts(s, ",meta");
+@@ -1035,17 +1042,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root)
+       }
+       if (args->ar_discard)
+               seq_puts(s, ",discard");
+-      val = sdp->sd_tune.gt_logd_secs;
+-      if (val != 30)
+-              seq_printf(s, ",commit=%d", val);
+-      val = sdp->sd_tune.gt_statfs_quantum;
+-      if (val != 30)
+-              seq_printf(s, ",statfs_quantum=%d", val);
+-      else if (sdp->sd_tune.gt_statfs_slow)
++      if (logd_secs != 30)
++              seq_printf(s, ",commit=%d", logd_secs);
++      if (statfs_quantum != 30)
++              seq_printf(s, ",statfs_quantum=%d", statfs_quantum);
++      else if (statfs_slow)
+               seq_puts(s, ",statfs_quantum=0");
+-      val = sdp->sd_tune.gt_quota_quantum;
+-      if (val != 60)
+-              seq_printf(s, ",quota_quantum=%d", val);
++      if (quota_quantum != 60)
++              seq_printf(s, ",quota_quantum=%d", quota_quantum);
+       if (args->ar_statfs_percent)
+               seq_printf(s, ",statfs_percent=%d", args->ar_statfs_percent);
+       if (args->ar_errors != GFS2_ERRORS_DEFAULT) {
+-- 
+2.40.1
+

diff --git a/queue-5.15/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch b/queue-5.15/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
new file mode 100644 (file)
index 0000000..658e83b
--- /dev/null
+++ b/queue-5.15/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
@@ -0,0 +1,54 @@
+From 8bd3d1e9637c39f72a2ff8a9574c410053d57cb3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 15:40:08 +0200
+Subject: HID: add quirk for 03f0:464a HP Elite Presenter Mouse
+
+From: Marco Morandini <marco.morandini@polimi.it>
+
+[ Upstream commit 0db117359e47750d8bd310d19f13e1c4ef7fc26a ]
+
+HP Elite Presenter Mouse HID Record Descriptor shows
+two mouses (Repord ID 0x1 and 0x2), one keypad (Report ID 0x5),
+two Consumer Controls (Report IDs 0x6 and 0x3).
+Previous to this commit it registers one mouse, one keypad
+and one Consumer Control, and it was usable only as a
+digitl laser pointer (one of the two mouses). This patch defines
+the 464a USB device ID and enables the HID_QUIRK_MULTI_INPUT
+quirk for it, allowing to use the device both as a mouse
+and a digital laser pointer.
+
+Signed-off-by: Marco Morandini <marco.morandini@polimi.it>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-ids.h    | 1 +
+ drivers/hid/hid-quirks.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
+index 5daec769df7ae..5fceefb3c707e 100644
+--- a/drivers/hid/hid-ids.h
++++ b/drivers/hid/hid-ids.h
+@@ -593,6 +593,7 @@
+ #define USB_DEVICE_ID_UGCI_FIGHTING   0x0030
+ 
+ #define USB_VENDOR_ID_HP              0x03f0
++#define USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A          0x464a
+ #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A 0x0a4a
+ #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a
+ #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE                0x134a
+diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
+index c7c06aa958c4d..96ca7d981ee20 100644
+--- a/drivers/hid/hid-quirks.c
++++ b/drivers/hid/hid-quirks.c
+@@ -96,6 +96,7 @@ static const struct hid_device_id hid_quirks[] = {
+       { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A096), HID_QUIRK_NO_INIT_REPORTS },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A293), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A), HID_QUIRK_ALWAYS_POLL },
++      { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A), HID_QUIRK_MULTI_INPUT },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL },
+-- 
+2.40.1
+

diff --git a/queue-5.15/hid-logitech-hidpp-add-usb-and-bluetooth-ids-for-the.patch b/queue-5.15/hid-logitech-hidpp-add-usb-and-bluetooth-ids-for-the.patch
new file mode 100644 (file)
index 0000000..7becd9f
--- /dev/null
+++ b/queue-5.15/hid-logitech-hidpp-add-usb-and-bluetooth-ids-for-the.patch
@@ -0,0 +1,46 @@
+From ea30c28f4707276b19730ac058b81d56d0793598 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 15:44:28 +0100
+Subject: HID: logitech-hidpp: Add USB and Bluetooth IDs for the Logitech G915
+ TKL Keyboard
+
+From: stuarthayhurst <stuart.a.hayhurst@gmail.com>
+
+[ Upstream commit 48aea8b445c422a372cf15915101035a47105421 ]
+
+Adds the USB and Bluetooth IDs for the Logitech G915 TKL keyboard, for device detection
+For this device, this provides battery reporting on top of hid-generic
+
+Reviewed-by: Bastien Nocera <hadess@hadess.net>
+Signed-off-by: Stuart Hayhurst <stuart.a.hayhurst@gmail.com>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-logitech-hidpp.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c
+index c61da859cd3c6..0ac67dd76574e 100644
+--- a/drivers/hid/hid-logitech-hidpp.c
++++ b/drivers/hid/hid-logitech-hidpp.c
+@@ -4377,6 +4377,8 @@ static const struct hid_device_id hidpp_devices[] = {
+         HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC086) },
+       { /* Logitech G903 Hero Gaming Mouse over USB */
+         HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC091) },
++      { /* Logitech G915 TKL Keyboard over USB */
++        HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC343) },
+       { /* Logitech G920 Wheel over USB */
+         HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G920_WHEEL),
+               .driver_data = HIDPP_QUIRK_CLASS_G920 | HIDPP_QUIRK_FORCE_OUTPUT_REPORTS},
+@@ -4392,6 +4394,8 @@ static const struct hid_device_id hidpp_devices[] = {
+       { /* MX5500 keyboard over Bluetooth */
+         HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb30b),
+         .driver_data = HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS },
++      { /* Logitech G915 TKL keyboard over Bluetooth */
++        HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb35f) },
+       { /* M-RCQ142 V470 Cordless Laser Mouse over Bluetooth */
+         HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb008) },
+       { /* MX Master mouse over Bluetooth */
+-- 
+2.40.1
+

diff --git a/queue-5.15/igc-read-before-write-to-srrctl-register.patch b/queue-5.15/igc-read-before-write-to-srrctl-register.patch
new file mode 100644 (file)
index 0000000..0f04635
--- /dev/null
+++ b/queue-5.15/igc-read-before-write-to-srrctl-register.patch
@@ -0,0 +1,96 @@
+From 3184abdc9131d206e062ce37d216468251ad2df6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 May 2023 08:48:06 -0700
+Subject: igc: read before write to SRRCTL register
+
+From: Song Yoong Siang <yoong.siang.song@intel.com>
+
+[ Upstream commit 3ce29c17dc847bf4245e16aad78a7617afa96297 ]
+
+igc_configure_rx_ring() function will be called as part of XDP program
+setup. If Rx hardware timestamp is enabled prio to XDP program setup,
+this timestamp enablement will be overwritten when buffer size is
+written into SRRCTL register.
+
+Thus, this commit read the register value before write to SRRCTL
+register. This commit is tested by using xdp_hw_metadata bpf selftest
+tool. The tool enables Rx hardware timestamp and then attach XDP program
+to igc driver. It will display hardware timestamp of UDP packet with
+port number 9092. Below are detail of test steps and results.
+
+Command on DUT:
+  sudo ./xdp_hw_metadata <interface name>
+
+Command on Link Partner:
+  echo -n skb | nc -u -q1 <destination IPv4 addr> 9092
+
+Result before this patch:
+  skb hwtstamp is not found!
+
+Result after this patch:
+  found skb hwtstamp = 1677800973.642836757
+
+Optionally, read PHC to confirm the values obtained are almost the same:
+Command:
+  sudo ./testptp -d /dev/ptp0 -g
+Result:
+  clock time: 1677800973.913598978 or Fri Mar  3 07:49:33 2023
+
+Fixes: fc9df2a0b520 ("igc: Enable RX via AF_XDP zero-copy")
+Cc: <stable@vger.kernel.org> # 5.14+
+Signed-off-by: Song Yoong Siang <yoong.siang.song@intel.com>
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Reviewed-by: Jesper Dangaard Brouer <brouer@redhat.com>
+Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
+Tested-by: Naama Meir <naamax.meir@linux.intel.com>
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/igc/igc_base.h | 11 ++++++++---
+ drivers/net/ethernet/intel/igc/igc_main.c |  7 +++++--
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h
+index ce530f5fd7bda..52849f5e8048d 100644
+--- a/drivers/net/ethernet/intel/igc/igc_base.h
++++ b/drivers/net/ethernet/intel/igc/igc_base.h
+@@ -85,8 +85,13 @@ union igc_adv_rx_desc {
+ #define IGC_RXDCTL_SWFLUSH            0x04000000 /* Receive Software Flush */
+ 
+ /* SRRCTL bit definitions */
+-#define IGC_SRRCTL_BSIZEPKT_SHIFT             10 /* Shift _right_ */
+-#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT         2  /* Shift _left_ */
+-#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF        0x02000000
++#define IGC_SRRCTL_BSIZEPKT_MASK      GENMASK(6, 0)
++#define IGC_SRRCTL_BSIZEPKT(x)                FIELD_PREP(IGC_SRRCTL_BSIZEPKT_MASK, \
++                                      (x) / 1024) /* in 1 KB resolution */
++#define IGC_SRRCTL_BSIZEHDR_MASK      GENMASK(13, 8)
++#define IGC_SRRCTL_BSIZEHDR(x)                FIELD_PREP(IGC_SRRCTL_BSIZEHDR_MASK, \
++                                      (x) / 64) /* in 64 bytes resolution */
++#define IGC_SRRCTL_DESCTYPE_MASK      GENMASK(27, 25)
++#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF        FIELD_PREP(IGC_SRRCTL_DESCTYPE_MASK, 1)
+ 
+ #endif /* _IGC_BASE_H */
+diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
+index a47dce10d3a78..a8c24a1c12b43 100644
+--- a/drivers/net/ethernet/intel/igc/igc_main.c
++++ b/drivers/net/ethernet/intel/igc/igc_main.c
+@@ -674,8 +674,11 @@ static void igc_configure_rx_ring(struct igc_adapter *adapter,
+       else
+               buf_size = IGC_RXBUFFER_2048;
+ 
+-      srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT;
+-      srrctl |= buf_size >> IGC_SRRCTL_BSIZEPKT_SHIFT;
++      srrctl = rd32(IGC_SRRCTL(reg_idx));
++      srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK |
++                  IGC_SRRCTL_DESCTYPE_MASK);
++      srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN);
++      srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size);
+       srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
+ 
+       wr32(IGC_SRRCTL(reg_idx), srrctl);
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-adc-stx104-implement-and-utilize-register-struct.patch b/queue-5.15/iio-adc-stx104-implement-and-utilize-register-struct.patch
new file mode 100644 (file)
index 0000000..786fb57
--- /dev/null
+++ b/queue-5.15/iio-adc-stx104-implement-and-utilize-register-struct.patch
@@ -0,0 +1,213 @@
+From 21f2016dac31bf754102a7288146d087ecdf3981 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Jul 2022 13:21:24 -0400
+Subject: iio: adc: stx104: Implement and utilize register structures
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 6cfd14c54b1f42f29097244c1b6208f8268d7d5b ]
+
+Reduce magic numbers and improve code readability by implementing and
+utilizing named register data structures.
+
+Tested-by: Fred Eckert <Frede@cmslaser.com>
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 74 +++++++++++++++++++++++++++-------------
+ 1 file changed, 50 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 7552351bfed9e..48a91a95e597b 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -16,6 +16,7 @@
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
+ #include <linux/spinlock.h>
++#include <linux/types.h>
+ 
+ #define STX104_OUT_CHAN(chan) {                               \
+       .type = IIO_VOLTAGE,                            \
+@@ -44,14 +45,36 @@ static unsigned int num_stx104;
+ module_param_hw_array(base, uint, ioport, &num_stx104, 0);
+ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
+ 
++/**
++ * struct stx104_reg - device register structure
++ * @ssr_ad:   Software Strobe Register and ADC Data
++ * @achan:    ADC Channel
++ * @dio:      Digital I/O
++ * @dac:      DAC Channels
++ * @cir_asr:  Clear Interrupts and ADC Status
++ * @acr:      ADC Control
++ * @pccr_fsh: Pacer Clock Control and FIFO Status MSB
++ * @acfg:     ADC Configuration
++ */
++struct stx104_reg {
++      u16 ssr_ad;
++      u8 achan;
++      u8 dio;
++      u16 dac[2];
++      u8 cir_asr;
++      u8 acr;
++      u8 pccr_fsh;
++      u8 acfg;
++};
++
+ /**
+  * struct stx104_iio - IIO device private data structure
+  * @chan_out_states:  channels' output states
+- * @base:             base port address of the IIO device
++ * @reg:              I/O address offset for the device registers
+  */
+ struct stx104_iio {
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+-      void __iomem *base;
++      struct stx104_reg __iomem *reg;
+ };
+ 
+ /**
+@@ -64,7 +87,7 @@ struct stx104_iio {
+ struct stx104_gpio {
+       struct gpio_chip chip;
+       spinlock_t lock;
+-      void __iomem *base;
++      u8 __iomem *base;
+       unsigned int out_state;
+ };
+ 
+@@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       struct iio_chan_spec const *chan, int *val, int *val2, long mask)
+ {
+       struct stx104_iio *const priv = iio_priv(indio_dev);
++      struct stx104_reg __iomem *const reg = priv->reg;
+       unsigned int adc_config;
+       int adbu;
+       int gain;
+@@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       switch (mask) {
+       case IIO_CHAN_INFO_HARDWAREGAIN:
+               /* get gain configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               gain = adc_config & 0x3;
+ 
+               *val = 1 << gain;
+@@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               }
+ 
+               /* select ADC channel */
+-              iowrite8(chan->channel | (chan->channel << 4), priv->base + 2);
++              iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
+ 
+-              /* trigger ADC sample capture and wait for completion */
+-              iowrite8(0, priv->base);
+-              while (ioread8(priv->base + 8) & BIT(7));
++              /* trigger ADC sample capture by writing to the 8-bit
++               * Software Strobe Register and wait for completion
++               */
++              iowrite8(0, &reg->ssr_ad);
++              while (ioread8(&reg->cir_asr) & BIT(7));
+ 
+-              *val = ioread16(priv->base);
++              *val = ioread16(&reg->ssr_ad);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               adbu = !(adc_config & BIT(2));
+ 
+               *val = -32768 * adbu;
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_SCALE:
+               /* get ADC bipolar/unipolar and gain configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               adbu = !(adc_config & BIT(2));
+               gain = adc_config & 0x3;
+ 
+@@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+               /* Only four gain states (x1, x2, x4, x8) */
+               switch (val) {
+               case 1:
+-                      iowrite8(0, priv->base + 11);
++                      iowrite8(0, &priv->reg->acfg);
+                       break;
+               case 2:
+-                      iowrite8(1, priv->base + 11);
++                      iowrite8(1, &priv->reg->acfg);
+                       break;
+               case 4:
+-                      iowrite8(2, priv->base + 11);
++                      iowrite8(2, &priv->reg->acfg);
+                       break;
+               case 8:
+-                      iowrite8(3, priv->base + 11);
++                      iowrite8(3, &priv->reg->acfg);
+                       break;
+               default:
+                       return -EINVAL;
+@@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                               return -EINVAL;
+ 
+                       priv->chan_out_states[chan->channel] = val;
+-                      iowrite16(val, priv->base + 4 + 2 * chan->channel);
++                      iowrite16(val, &priv->reg->dac[chan->channel]);
+ 
+                       return 0;
+               }
+@@ -307,15 +333,15 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       }
+ 
+       priv = iio_priv(indio_dev);
+-      priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT);
+-      if (!priv->base)
++      priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
++      if (!priv->reg)
+               return -ENOMEM;
+ 
+       indio_dev->info = &stx104_info;
+       indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+       /* determine if differential inputs */
+-      if (ioread8(priv->base + 8) & BIT(5)) {
++      if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
+               indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
+               indio_dev->channels = stx104_channels_diff;
+       } else {
+@@ -326,14 +352,14 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       indio_dev->name = dev_name(dev);
+ 
+       /* configure device for software trigger operation */
+-      iowrite8(0, priv->base + 9);
++      iowrite8(0, &priv->reg->acr);
+ 
+       /* initialize gain setting to x1 */
+-      iowrite8(0, priv->base + 11);
++      iowrite8(0, &priv->reg->acfg);
+ 
+       /* initialize DAC output to 0V */
+-      iowrite16(0, priv->base + 4);
+-      iowrite16(0, priv->base + 6);
++      iowrite16(0, &priv->reg->dac[0]);
++      iowrite16(0, &priv->reg->dac[1]);
+ 
+       stx104gpio->chip.label = dev_name(dev);
+       stx104gpio->chip.parent = dev;
+@@ -348,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
+       stx104gpio->chip.set = stx104_gpio_set;
+       stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
+-      stx104gpio->base = priv->base + 3;
++      stx104gpio->base = &priv->reg->dio;
+       stx104gpio->out_state = 0x0;
+ 
+       spin_lock_init(&stx104gpio->lock);
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-adc-stx104-utilize-iomap-interface.patch b/queue-5.15/iio-adc-stx104-utilize-iomap-interface.patch
new file mode 100644 (file)
index 0000000..8c400ac
--- /dev/null
+++ b/queue-5.15/iio-adc-stx104-utilize-iomap-interface.patch
@@ -0,0 +1,206 @@
+From f0c1b7fa9eea01c9bdb85438c745adbf14056bc3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 May 2022 13:30:59 -0400
+Subject: iio: adc: stx104: Utilize iomap interface
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 73b8390cc27e096ab157be261ccc4eaaa6db87af ]
+
+This driver doesn't need to access I/O ports directly via inb()/outb()
+and friends. This patch abstracts such access by calling ioport_map()
+to enable the use of more typical ioread8()/iowrite8() I/O memory
+accessor calls.
+
+Suggested-by: David Laight <David.Laight@ACULAB.COM>
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/64673797df382c52fc32fce24348b25a0b05e73a.1652201921.git.william.gray@linaro.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 56 +++++++++++++++++++++-------------------
+ 1 file changed, 29 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 55bd2dc514e93..7552351bfed9e 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -51,7 +51,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
+  */
+ struct stx104_iio {
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+-      unsigned int base;
++      void __iomem *base;
+ };
+ 
+ /**
+@@ -64,7 +64,7 @@ struct stx104_iio {
+ struct stx104_gpio {
+       struct gpio_chip chip;
+       spinlock_t lock;
+-      unsigned int base;
++      void __iomem *base;
+       unsigned int out_state;
+ };
+ 
+@@ -79,7 +79,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       switch (mask) {
+       case IIO_CHAN_INFO_HARDWAREGAIN:
+               /* get gain configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               gain = adc_config & 0x3;
+ 
+               *val = 1 << gain;
+@@ -91,24 +91,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               }
+ 
+               /* select ADC channel */
+-              outb(chan->channel | (chan->channel << 4), priv->base + 2);
++              iowrite8(chan->channel | (chan->channel << 4), priv->base + 2);
+ 
+               /* trigger ADC sample capture and wait for completion */
+-              outb(0, priv->base);
+-              while (inb(priv->base + 8) & BIT(7));
++              iowrite8(0, priv->base);
++              while (ioread8(priv->base + 8) & BIT(7));
+ 
+-              *val = inw(priv->base);
++              *val = ioread16(priv->base);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               adbu = !(adc_config & BIT(2));
+ 
+               *val = -32768 * adbu;
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_SCALE:
+               /* get ADC bipolar/unipolar and gain configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               adbu = !(adc_config & BIT(2));
+               gain = adc_config & 0x3;
+ 
+@@ -130,16 +130,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+               /* Only four gain states (x1, x2, x4, x8) */
+               switch (val) {
+               case 1:
+-                      outb(0, priv->base + 11);
++                      iowrite8(0, priv->base + 11);
+                       break;
+               case 2:
+-                      outb(1, priv->base + 11);
++                      iowrite8(1, priv->base + 11);
+                       break;
+               case 4:
+-                      outb(2, priv->base + 11);
++                      iowrite8(2, priv->base + 11);
+                       break;
+               case 8:
+-                      outb(3, priv->base + 11);
++                      iowrite8(3, priv->base + 11);
+                       break;
+               default:
+                       return -EINVAL;
+@@ -153,7 +153,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                               return -EINVAL;
+ 
+                       priv->chan_out_states[chan->channel] = val;
+-                      outw(val, priv->base + 4 + 2 * chan->channel);
++                      iowrite16(val, priv->base + 4 + 2 * chan->channel);
+ 
+                       return 0;
+               }
+@@ -222,7 +222,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset)
+       if (offset >= 4)
+               return -EINVAL;
+ 
+-      return !!(inb(stx104gpio->base) & BIT(offset));
++      return !!(ioread8(stx104gpio->base) & BIT(offset));
+ }
+ 
+ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+@@ -230,7 +230,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+ {
+       struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
+ 
+-      *bits = inb(stx104gpio->base);
++      *bits = ioread8(stx104gpio->base);
+ 
+       return 0;
+ }
+@@ -252,7 +252,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset,
+       else
+               stx104gpio->out_state &= ~mask;
+ 
+-      outb(stx104gpio->out_state, stx104gpio->base);
++      iowrite8(stx104gpio->out_state, stx104gpio->base);
+ 
+       spin_unlock_irqrestore(&stx104gpio->lock, flags);
+ }
+@@ -279,7 +279,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip,
+ 
+       stx104gpio->out_state &= ~*mask;
+       stx104gpio->out_state |= *mask & *bits;
+-      outb(stx104gpio->out_state, stx104gpio->base);
++      iowrite8(stx104gpio->out_state, stx104gpio->base);
+ 
+       spin_unlock_irqrestore(&stx104gpio->lock, flags);
+ }
+@@ -306,11 +306,16 @@ static int stx104_probe(struct device *dev, unsigned int id)
+               return -EBUSY;
+       }
+ 
++      priv = iio_priv(indio_dev);
++      priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT);
++      if (!priv->base)
++              return -ENOMEM;
++
+       indio_dev->info = &stx104_info;
+       indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+       /* determine if differential inputs */
+-      if (inb(base[id] + 8) & BIT(5)) {
++      if (ioread8(priv->base + 8) & BIT(5)) {
+               indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
+               indio_dev->channels = stx104_channels_diff;
+       } else {
+@@ -320,18 +325,15 @@ static int stx104_probe(struct device *dev, unsigned int id)
+ 
+       indio_dev->name = dev_name(dev);
+ 
+-      priv = iio_priv(indio_dev);
+-      priv->base = base[id];
+-
+       /* configure device for software trigger operation */
+-      outb(0, base[id] + 9);
++      iowrite8(0, priv->base + 9);
+ 
+       /* initialize gain setting to x1 */
+-      outb(0, base[id] + 11);
++      iowrite8(0, priv->base + 11);
+ 
+       /* initialize DAC output to 0V */
+-      outw(0, base[id] + 4);
+-      outw(0, base[id] + 6);
++      iowrite16(0, priv->base + 4);
++      iowrite16(0, priv->base + 6);
+ 
+       stx104gpio->chip.label = dev_name(dev);
+       stx104gpio->chip.parent = dev;
+@@ -346,7 +348,7 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
+       stx104gpio->chip.set = stx104_gpio_set;
+       stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
+-      stx104gpio->base = base[id] + 3;
++      stx104gpio->base = priv->base + 3;
+       stx104gpio->out_state = 0x0;
+ 
+       spin_lock_init(&stx104gpio->lock);
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-add-addac-subdirectory.patch b/queue-5.15/iio-add-addac-subdirectory.patch
new file mode 100644 (file)
index 0000000..25fa303
--- /dev/null
+++ b/queue-5.15/iio-add-addac-subdirectory.patch
@@ -0,0 +1,78 @@
+From b686706b64df4c9ef9951d6086400938d029f6d6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 5 Dec 2021 13:40:43 +0200
+Subject: iio: add addac subdirectory
+
+From: Cosmin Tanislav <demonsingur@gmail.com>
+
+[ Upstream commit b62e2e1763cda3a6c494ed754317f19be1249297 ]
+
+For IIO devices that expose both ADC and DAC functionality.
+
+Signed-off-by: Cosmin Tanislav <cosmin.tanislav@analog.com>
+Link: https://lore.kernel.org/r/20211205114045.173612-2-cosmin.tanislav@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/Kconfig        | 1 +
+ drivers/iio/Makefile       | 1 +
+ drivers/iio/addac/Kconfig  | 8 ++++++++
+ drivers/iio/addac/Makefile | 6 ++++++
+ 4 files changed, 16 insertions(+)
+ create mode 100644 drivers/iio/addac/Kconfig
+ create mode 100644 drivers/iio/addac/Makefile
+
+diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
+index 2334ad249b462..4fb4321a72cb1 100644
+--- a/drivers/iio/Kconfig
++++ b/drivers/iio/Kconfig
+@@ -70,6 +70,7 @@ config IIO_TRIGGERED_EVENT
+ 
+ source "drivers/iio/accel/Kconfig"
+ source "drivers/iio/adc/Kconfig"
++source "drivers/iio/addac/Kconfig"
+ source "drivers/iio/afe/Kconfig"
+ source "drivers/iio/amplifiers/Kconfig"
+ source "drivers/iio/cdc/Kconfig"
+diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
+index 65e39bd4f9346..8d48c70fee4d3 100644
+--- a/drivers/iio/Makefile
++++ b/drivers/iio/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_IIO_TRIGGERED_EVENT) += industrialio-triggered-event.o
+ 
+ obj-y += accel/
+ obj-y += adc/
++obj-y += addac/
+ obj-y += afe/
+ obj-y += amplifiers/
+ obj-y += buffer/
+diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig
+new file mode 100644
+index 0000000000000..2e64d7755d5ea
+--- /dev/null
++++ b/drivers/iio/addac/Kconfig
+@@ -0,0 +1,8 @@
++#
++# ADC DAC drivers
++#
++# When adding new entries keep the list in alphabetical order
++
++menu "Analog to digital and digital to analog converters"
++
++endmenu
+diff --git a/drivers/iio/addac/Makefile b/drivers/iio/addac/Makefile
+new file mode 100644
+index 0000000000000..b888b9ee12da0
+--- /dev/null
++++ b/drivers/iio/addac/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# Makefile for industrial I/O ADDAC drivers
++#
++
++# When adding new entries keep the list in alphabetical order
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-addac-stx104-fix-race-condition-for-stx104_write.patch b/queue-5.15/iio-addac-stx104-fix-race-condition-for-stx104_write.patch
new file mode 100644 (file)
index 0000000..1570f69
--- /dev/null
+++ b/queue-5.15/iio-addac-stx104-fix-race-condition-for-stx104_write.patch
@@ -0,0 +1,74 @@
+From 67268938ae0b5753f70070c05c8b85d8922171dd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Apr 2023 10:40:10 -0400
+Subject: iio: addac: stx104: Fix race condition for stx104_write_raw()
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 9740827468cea80c42db29e7171a50e99acf7328 ]
+
+The priv->chan_out_states array and actual DAC value can become
+mismatched if stx104_write_raw() is called concurrently. Prevent such a
+race condition by utilizing a mutex.
+
+Fixes: 97a445dad37a ("iio: Add IIO support for the DAC on the Apex Embedded Systems STX104")
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/c95c9a77fcef36b2a052282146950f23bbc1ebdc.1680790580.git.william.gray@linaro.org
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/addac/stx104.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c
+index 48a91a95e597b..e110a910235ff 100644
+--- a/drivers/iio/addac/stx104.c
++++ b/drivers/iio/addac/stx104.c
+@@ -15,6 +15,7 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
++#include <linux/mutex.h>
+ #include <linux/spinlock.h>
+ #include <linux/types.h>
+ 
+@@ -69,10 +70,12 @@ struct stx104_reg {
+ 
+ /**
+  * struct stx104_iio - IIO device private data structure
++ * @lock: synchronization lock to prevent I/O race conditions
+  * @chan_out_states:  channels' output states
+  * @reg:              I/O address offset for the device registers
+  */
+ struct stx104_iio {
++      struct mutex lock;
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+       struct stx104_reg __iomem *reg;
+ };
+@@ -178,9 +181,12 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                       if ((unsigned int)val > 65535)
+                               return -EINVAL;
+ 
++                      mutex_lock(&priv->lock);
++
+                       priv->chan_out_states[chan->channel] = val;
+                       iowrite16(val, &priv->reg->dac[chan->channel]);
+ 
++                      mutex_unlock(&priv->lock);
+                       return 0;
+               }
+               return -EINVAL;
+@@ -351,6 +357,8 @@ static int stx104_probe(struct device *dev, unsigned int id)
+ 
+       indio_dev->name = dev_name(dev);
+ 
++      mutex_init(&priv->lock);
++
+       /* configure device for software trigger operation */
+       iowrite8(0, &priv->reg->acr);
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-addac-stx104-fix-race-condition-when-converting-.patch b/queue-5.15/iio-addac-stx104-fix-race-condition-when-converting-.patch
new file mode 100644 (file)
index 0000000..12cf915
--- /dev/null
+++ b/queue-5.15/iio-addac-stx104-fix-race-condition-when-converting-.patch
@@ -0,0 +1,50 @@
+From aa5968cd17ea84586a6a16d9481ae83550762523 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Apr 2023 10:40:11 -0400
+Subject: iio: addac: stx104: Fix race condition when converting
+ analog-to-digital
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 4f9b80aefb9e2f542a49d9ec087cf5919730e1dd ]
+
+The ADC conversion procedure requires several device I/O operations
+performed in a particular sequence. If stx104_read_raw() is called
+concurrently, the ADC conversion procedure could be clobbered. Prevent
+such a race condition by utilizing a mutex.
+
+Fixes: 4075a283ae83 ("iio: stx104: Add IIO support for the ADC channels")
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/2ae5e40eed5006ca735e4c12181a9ff5ced65547.1680790580.git.william.gray@linaro.org
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/addac/stx104.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c
+index e110a910235ff..b658a75d4e3a8 100644
+--- a/drivers/iio/addac/stx104.c
++++ b/drivers/iio/addac/stx104.c
+@@ -117,6 +117,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+                       return IIO_VAL_INT;
+               }
+ 
++              mutex_lock(&priv->lock);
++
+               /* select ADC channel */
+               iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
+ 
+@@ -127,6 +129,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               while (ioread8(&reg->cir_asr) & BIT(7));
+ 
+               *val = ioread16(&reg->ssr_ad);
++
++              mutex_unlock(&priv->lock);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-- 
+2.40.1
+

diff --git a/queue-5.15/iio-stx104-move-to-addac-subdirectory.patch b/queue-5.15/iio-stx104-move-to-addac-subdirectory.patch
new file mode 100644 (file)
index 0000000..5b1310b
--- /dev/null
+++ b/queue-5.15/iio-stx104-move-to-addac-subdirectory.patch
@@ -0,0 +1,119 @@
+From 1d70961b791230a2dfa0f4d65c9cb9bb94d1eb64 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 18:29:21 -0400
+Subject: iio: stx104: Move to addac subdirectory
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 955c2aa9cff2dd07ff798ca8c883398731687972 ]
+
+The stx104 driver supports both ADC and DAC functionality.
+
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/20220815222921.138945-1-william.gray@linaro.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ MAINTAINERS                         |  2 +-
+ drivers/iio/adc/Kconfig             | 16 ----------------
+ drivers/iio/adc/Makefile            |  1 -
+ drivers/iio/addac/Kconfig           | 16 ++++++++++++++++
+ drivers/iio/addac/Makefile          |  1 +
+ drivers/iio/{adc => addac}/stx104.c |  0
+ 6 files changed, 18 insertions(+), 18 deletions(-)
+ rename drivers/iio/{adc => addac}/stx104.c (100%)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index e6b53e76651be..9216b9c85ce92 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1250,7 +1250,7 @@ APEX EMBEDDED SYSTEMS STX104 IIO DRIVER
+ M:    William Breathitt Gray <vilhelm.gray@gmail.com>
+ L:    linux-iio@vger.kernel.org
+ S:    Maintained
+-F:    drivers/iio/adc/stx104.c
++F:    drivers/iio/addac/stx104.c
+ 
+ APM DRIVER
+ M:    Jiri Kosina <jikos@kernel.org>
+diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
+index af168e1c9fdb5..86b83dc7b7d99 100644
+--- a/drivers/iio/adc/Kconfig
++++ b/drivers/iio/adc/Kconfig
+@@ -991,22 +991,6 @@ config STMPE_ADC
+         Say yes here to build support for ST Microelectronics STMPE
+         built-in ADC block (stmpe811).
+ 
+-config STX104
+-      tristate "Apex Embedded Systems STX104 driver"
+-      depends on PC104 && X86
+-      select ISA_BUS_API
+-      select GPIOLIB
+-      help
+-        Say yes here to build support for the Apex Embedded Systems STX104
+-        integrated analog PC/104 card.
+-
+-        This driver supports the 16 channels of single-ended (8 channels of
+-        differential) analog inputs, 2 channels of analog output, 4 digital
+-        inputs, and 4 digital outputs provided by the STX104.
+-
+-        The base port addresses for the devices may be configured via the base
+-        array module parameter.
+-
+ config SUN4I_GPADC
+       tristate "Support for the Allwinner SoCs GPADC"
+       depends on IIO
+diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
+index d68550f493e34..13668c4cfbaf6 100644
+--- a/drivers/iio/adc/Makefile
++++ b/drivers/iio/adc/Makefile
+@@ -85,7 +85,6 @@ obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
+ obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
+ obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
+ obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
+-obj-$(CONFIG_STX104) += stx104.o
+ obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
+ obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
+ obj-$(CONFIG_STM32_ADC) += stm32-adc.o
+diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig
+index 2e64d7755d5ea..1f598670e84fb 100644
+--- a/drivers/iio/addac/Kconfig
++++ b/drivers/iio/addac/Kconfig
+@@ -5,4 +5,20 @@
+ 
+ menu "Analog to digital and digital to analog converters"
+ 
++config STX104
++      tristate "Apex Embedded Systems STX104 driver"
++      depends on PC104 && X86
++      select ISA_BUS_API
++      select GPIOLIB
++      help
++        Say yes here to build support for the Apex Embedded Systems STX104
++        integrated analog PC/104 card.
++
++        This driver supports the 16 channels of single-ended (8 channels of
++        differential) analog inputs, 2 channels of analog output, 4 digital
++        inputs, and 4 digital outputs provided by the STX104.
++
++        The base port addresses for the devices may be configured via the base
++        array module parameter.
++
+ endmenu
+diff --git a/drivers/iio/addac/Makefile b/drivers/iio/addac/Makefile
+index b888b9ee12da0..8629145233544 100644
+--- a/drivers/iio/addac/Makefile
++++ b/drivers/iio/addac/Makefile
+@@ -4,3 +4,4 @@
+ #
+ 
+ # When adding new entries keep the list in alphabetical order
++obj-$(CONFIG_STX104) += stx104.o
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/addac/stx104.c
+similarity index 100%
+rename from drivers/iio/adc/stx104.c
+rename to drivers/iio/addac/stx104.c
+-- 
+2.40.1
+

diff --git a/queue-5.15/iopoll-call-cpu_relax-in-busy-loops.patch b/queue-5.15/iopoll-call-cpu_relax-in-busy-loops.patch
new file mode 100644 (file)
index 0000000..2f40370
--- /dev/null
+++ b/queue-5.15/iopoll-call-cpu_relax-in-busy-loops.patch
@@ -0,0 +1,77 @@
+From 0c7aaa6b3f97f8ed9ab0a3a47b2e74603ad68396 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Jun 2023 10:50:36 +0200
+Subject: iopoll: Call cpu_relax() in busy loops
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+[ Upstream commit b407460ee99033503993ac7437d593451fcdfe44 ]
+
+It is considered good practice to call cpu_relax() in busy loops, see
+Documentation/process/volatile-considered-harmful.rst.  This can not
+only lower CPU power consumption or yield to a hyperthreaded twin
+processor, but also allows an architecture to mitigate hardware issues
+(e.g. ARM Erratum 754327 for Cortex-A9 prior to r2p0) in the
+architecture-specific cpu_relax() implementation.
+
+In addition, cpu_relax() is also a compiler barrier.  It is not
+immediately obvious that the @op argument "function" will result in an
+actual function call (e.g. in case of inlining).
+
+Where a function call is a C sequence point, this is lost on inlining.
+Therefore, with agressive enough optimization it might be possible for
+the compiler to hoist the:
+
+        (val) = op(args);
+
+"load" out of the loop because it doesn't see the value changing. The
+addition of cpu_relax() would inhibit this.
+
+As the iopoll helpers lack calls to cpu_relax(), people are sometimes
+reluctant to use them, and may fall back to open-coded polling loops
+(including cpu_relax() calls) instead.
+
+Fix this by adding calls to cpu_relax() to the iopoll helpers:
+  - For the non-atomic case, it is sufficient to call cpu_relax() in
+    case of a zero sleep-between-reads value, as a call to
+    usleep_range() is a safe barrier otherwise.  However, it doesn't
+    hurt to add the call regardless, for simplicity, and for similarity
+    with the atomic case below.
+  - For the atomic case, cpu_relax() must be called regardless of the
+    sleep-between-reads value, as there is no guarantee all
+    architecture-specific implementations of udelay() handle this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Link: https://lore.kernel.org/r/45c87bec3397fdd704376807f0eec5cc71be440f.1685692810.git.geert+renesas@glider.be
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/iopoll.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
+index 2c8860e406bd8..0417360a6db9b 100644
+--- a/include/linux/iopoll.h
++++ b/include/linux/iopoll.h
+@@ -53,6 +53,7 @@
+               } \
+               if (__sleep_us) \
+                       usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
++              cpu_relax(); \
+       } \
+       (cond) ? 0 : -ETIMEDOUT; \
+ })
+@@ -95,6 +96,7 @@
+               } \
+               if (__delay_us) \
+                       udelay(__delay_us); \
++              cpu_relax(); \
+       } \
+       (cond) ? 0 : -ETIMEDOUT; \
+ })
+-- 
+2.40.1
+

diff --git a/queue-5.15/macsec-fix-traffic-counters-statistics.patch b/queue-5.15/macsec-fix-traffic-counters-statistics.patch
new file mode 100644 (file)
index 0000000..6efc6b2
--- /dev/null
+++ b/queue-5.15/macsec-fix-traffic-counters-statistics.patch
@@ -0,0 +1,250 @@
+From 8dd30d8ad5c91bb8a7c7cb24cd536ecfafae9a13 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Aug 2022 15:38:23 -0700
+Subject: macsec: Fix traffic counters/statistics
+
+From: Clayton Yager <Clayton_Yager@selinc.com>
+
+[ Upstream commit 91ec9bd57f3524ff3d86bfb7c9ee5a315019733c ]
+
+OutOctetsProtected, OutOctetsEncrypted, InOctetsValidated, and
+InOctetsDecrypted were incrementing by the total number of octets in frames
+instead of by the number of octets of User Data in frames.
+
+The Controlled Port statistics ifOutOctets and ifInOctets were incrementing
+by the total number of octets instead of the number of octets of the MSDUs
+plus octets of the destination and source MAC addresses.
+
+The Controlled Port statistics ifInDiscards and ifInErrors were not
+incrementing each time the counters they aggregate were.
+
+The Controlled Port statistic ifInErrors was not included in the output of
+macsec_get_stats64 so the value was not present in ip commands output.
+
+The ReceiveSA counters InPktsNotValid, InPktsNotUsingSA, and InPktsUnusedSA
+were not incrementing.
+
+Signed-off-by: Clayton Yager <Clayton_Yager@selinc.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Stable-dep-of: 32d0a49d36a2 ("macsec: use DEV_STATS_INC()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/macsec.c | 58 +++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 49 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
+index 10b3f4fb2612c..e7af0e7a29678 100644
+--- a/drivers/net/macsec.c
++++ b/drivers/net/macsec.c
+@@ -160,6 +160,19 @@ static struct macsec_rx_sa *macsec_rxsa_get(struct macsec_rx_sa __rcu *ptr)
+       return sa;
+ }
+ 
++static struct macsec_rx_sa *macsec_active_rxsa_get(struct macsec_rx_sc *rx_sc)
++{
++      struct macsec_rx_sa *sa = NULL;
++      int an;
++
++      for (an = 0; an < MACSEC_NUM_AN; an++)  {
++              sa = macsec_rxsa_get(rx_sc->sa[an]);
++              if (sa)
++                      break;
++      }
++      return sa;
++}
++
+ static void free_rx_sc_rcu(struct rcu_head *head)
+ {
+       struct macsec_rx_sc *rx_sc = container_of(head, struct macsec_rx_sc, rcu_head);
+@@ -493,18 +506,28 @@ static void macsec_encrypt_finish(struct sk_buff *skb, struct net_device *dev)
+       skb->protocol = eth_hdr(skb)->h_proto;
+ }
+ 
++static unsigned int macsec_msdu_len(struct sk_buff *skb)
++{
++      struct macsec_dev *macsec = macsec_priv(skb->dev);
++      struct macsec_secy *secy = &macsec->secy;
++      bool sci_present = macsec_skb_cb(skb)->has_sci;
++
++      return skb->len - macsec_hdr_len(sci_present) - secy->icv_len;
++}
++
+ static void macsec_count_tx(struct sk_buff *skb, struct macsec_tx_sc *tx_sc,
+                           struct macsec_tx_sa *tx_sa)
+ {
++      unsigned int msdu_len = macsec_msdu_len(skb);
+       struct pcpu_tx_sc_stats *txsc_stats = this_cpu_ptr(tx_sc->stats);
+ 
+       u64_stats_update_begin(&txsc_stats->syncp);
+       if (tx_sc->encrypt) {
+-              txsc_stats->stats.OutOctetsEncrypted += skb->len;
++              txsc_stats->stats.OutOctetsEncrypted += msdu_len;
+               txsc_stats->stats.OutPktsEncrypted++;
+               this_cpu_inc(tx_sa->stats->OutPktsEncrypted);
+       } else {
+-              txsc_stats->stats.OutOctetsProtected += skb->len;
++              txsc_stats->stats.OutOctetsProtected += msdu_len;
+               txsc_stats->stats.OutPktsProtected++;
+               this_cpu_inc(tx_sa->stats->OutPktsProtected);
+       }
+@@ -534,9 +557,10 @@ static void macsec_encrypt_done(struct crypto_async_request *base, int err)
+       aead_request_free(macsec_skb_cb(skb)->req);
+ 
+       rcu_read_lock_bh();
+-      macsec_encrypt_finish(skb, dev);
+       macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa);
+-      len = skb->len;
++      /* packet is encrypted/protected so tx_bytes must be calculated */
++      len = macsec_msdu_len(skb) + 2 * ETH_ALEN;
++      macsec_encrypt_finish(skb, dev);
+       ret = dev_queue_xmit(skb);
+       count_tx(dev, ret, len);
+       rcu_read_unlock_bh();
+@@ -695,6 +719,7 @@ static struct sk_buff *macsec_encrypt(struct sk_buff *skb,
+ 
+       macsec_skb_cb(skb)->req = req;
+       macsec_skb_cb(skb)->tx_sa = tx_sa;
++      macsec_skb_cb(skb)->has_sci = sci_present;
+       aead_request_set_callback(req, 0, macsec_encrypt_done, skb);
+ 
+       dev_hold(skb->dev);
+@@ -736,15 +761,17 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsLate++;
+               u64_stats_update_end(&rxsc_stats->syncp);
++              secy->netdev->stats.rx_dropped++;
+               return false;
+       }
+ 
+       if (secy->validate_frames != MACSEC_VALIDATE_DISABLED) {
++              unsigned int msdu_len = macsec_msdu_len(skb);
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               if (hdr->tci_an & MACSEC_TCI_E)
+-                      rxsc_stats->stats.InOctetsDecrypted += skb->len;
++                      rxsc_stats->stats.InOctetsDecrypted += msdu_len;
+               else
+-                      rxsc_stats->stats.InOctetsValidated += skb->len;
++                      rxsc_stats->stats.InOctetsValidated += msdu_len;
+               u64_stats_update_end(&rxsc_stats->syncp);
+       }
+ 
+@@ -757,6 +784,8 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotValid++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      this_cpu_inc(rx_sa->stats->InPktsNotValid);
++                      secy->netdev->stats.rx_errors++;
+                       return false;
+               }
+ 
+@@ -849,9 +878,9 @@ static void macsec_decrypt_done(struct crypto_async_request *base, int err)
+ 
+       macsec_finalize_skb(skb, macsec->secy.icv_len,
+                           macsec_extra_len(macsec_skb_cb(skb)->has_sci));
++      len = skb->len;
+       macsec_reset_skb(skb, macsec->secy.netdev);
+ 
+-      len = skb->len;
+       if (gro_cells_receive(&macsec->gro_cells, skb) == NET_RX_SUCCESS)
+               count_rx(dev, len);
+ 
+@@ -1042,6 +1071,7 @@ static enum rx_handler_result handle_not_macsec(struct sk_buff *skb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoTag++;
+                       u64_stats_update_end(&secy_stats->syncp);
++                      macsec->secy.netdev->stats.rx_dropped++;
+                       continue;
+               }
+ 
+@@ -1151,6 +1181,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&secy_stats->syncp);
+               secy_stats->stats.InPktsBadTag++;
+               u64_stats_update_end(&secy_stats->syncp);
++              secy->netdev->stats.rx_errors++;
+               goto drop_nosa;
+       }
+ 
+@@ -1161,11 +1192,15 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               /* If validateFrames is Strict or the C bit in the
+                * SecTAG is set, discard
+                */
++              struct macsec_rx_sa *active_rx_sa = macsec_active_rxsa_get(rx_sc);
+               if (hdr->tci_an & MACSEC_TCI_C ||
+                   secy->validate_frames == MACSEC_VALIDATE_STRICT) {
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotUsingSA++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      secy->netdev->stats.rx_errors++;
++                      if (active_rx_sa)
++                              this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA);
+                       goto drop_nosa;
+               }
+ 
+@@ -1175,6 +1210,8 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsUnusedSA++;
+               u64_stats_update_end(&rxsc_stats->syncp);
++              if (active_rx_sa)
++                      this_cpu_inc(active_rx_sa->stats->InPktsUnusedSA);
+               goto deliver;
+       }
+ 
+@@ -1195,6 +1232,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsLate++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      macsec->secy.netdev->stats.rx_dropped++;
+                       goto drop;
+               }
+       }
+@@ -1223,6 +1261,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+ deliver:
+       macsec_finalize_skb(skb, secy->icv_len,
+                           macsec_extra_len(macsec_skb_cb(skb)->has_sci));
++      len = skb->len;
+       macsec_reset_skb(skb, secy->netdev);
+ 
+       if (rx_sa)
+@@ -1230,7 +1269,6 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+       macsec_rxsc_put(rx_sc);
+ 
+       skb_orphan(skb);
+-      len = skb->len;
+       ret = gro_cells_receive(&macsec->gro_cells, skb);
+       if (ret == NET_RX_SUCCESS)
+               count_rx(dev, len);
+@@ -1272,6 +1310,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
++                      macsec->secy.netdev->stats.rx_errors++;
+                       continue;
+               }
+ 
+@@ -3403,6 +3442,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+               return NETDEV_TX_OK;
+       }
+ 
++      len = skb->len;
+       skb = macsec_encrypt(skb, dev);
+       if (IS_ERR(skb)) {
+               if (PTR_ERR(skb) != -EINPROGRESS)
+@@ -3413,7 +3453,6 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+       macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa);
+ 
+       macsec_encrypt_finish(skb, dev);
+-      len = skb->len;
+       ret = dev_queue_xmit(skb);
+       count_tx(dev, ret, len);
+       return ret;
+@@ -3643,6 +3682,7 @@ static void macsec_get_stats64(struct net_device *dev,
+ 
+       s->rx_dropped = dev->stats.rx_dropped;
+       s->tx_dropped = dev->stats.tx_dropped;
++      s->rx_errors = dev->stats.rx_errors;
+ }
+ 
+ static int macsec_get_iflink(const struct net_device *dev)
+-- 
+2.40.1
+

diff --git a/queue-5.15/macsec-use-dev_stats_inc.patch b/queue-5.15/macsec-use-dev_stats_inc.patch
new file mode 100644 (file)
index 0000000..c9273cc
--- /dev/null
+++ b/queue-5.15/macsec-use-dev_stats_inc.patch
@@ -0,0 +1,145 @@
+From f09d0f20c5bd2f9a941b1dc9a67938ef87813e00 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 4 Aug 2023 17:26:52 +0000
+Subject: macsec: use DEV_STATS_INC()
+
+From: Eric Dumazet <edumazet@google.com>
+
+[ Upstream commit 32d0a49d36a2a306c2e47fe5659361e424f0ed3f ]
+
+syzbot/KCSAN reported data-races in macsec whenever dev->stats fields
+are updated.
+
+It appears all of these updates can happen from multiple cpus.
+
+Adopt SMP safe DEV_STATS_INC() to update dev->stats fields.
+
+Fixes: c09440f7dcb3 ("macsec: introduce IEEE 802.1AE driver")
+Reported-by: syzbot <syzkaller@googlegroups.com>
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Cc: Sabrina Dubroca <sd@queasysnail.net>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/macsec.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
+index e7af0e7a29678..98ce24422424c 100644
+--- a/drivers/net/macsec.c
++++ b/drivers/net/macsec.c
+@@ -761,7 +761,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsLate++;
+               u64_stats_update_end(&rxsc_stats->syncp);
+-              secy->netdev->stats.rx_dropped++;
++              DEV_STATS_INC(secy->netdev, rx_dropped);
+               return false;
+       }
+ 
+@@ -785,7 +785,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+                       rxsc_stats->stats.InPktsNotValid++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+                       this_cpu_inc(rx_sa->stats->InPktsNotValid);
+-                      secy->netdev->stats.rx_errors++;
++                      DEV_STATS_INC(secy->netdev, rx_errors);
+                       return false;
+               }
+ 
+@@ -1071,7 +1071,7 @@ static enum rx_handler_result handle_not_macsec(struct sk_buff *skb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoTag++;
+                       u64_stats_update_end(&secy_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+                       continue;
+               }
+ 
+@@ -1181,7 +1181,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&secy_stats->syncp);
+               secy_stats->stats.InPktsBadTag++;
+               u64_stats_update_end(&secy_stats->syncp);
+-              secy->netdev->stats.rx_errors++;
++              DEV_STATS_INC(secy->netdev, rx_errors);
+               goto drop_nosa;
+       }
+ 
+@@ -1198,7 +1198,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotUsingSA++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+-                      secy->netdev->stats.rx_errors++;
++                      DEV_STATS_INC(secy->netdev, rx_errors);
+                       if (active_rx_sa)
+                               this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA);
+                       goto drop_nosa;
+@@ -1232,7 +1232,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsLate++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+                       goto drop;
+               }
+       }
+@@ -1273,7 +1273,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+       if (ret == NET_RX_SUCCESS)
+               count_rx(dev, len);
+       else
+-              macsec->secy.netdev->stats.rx_dropped++;
++              DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+ 
+       rcu_read_unlock();
+ 
+@@ -1310,7 +1310,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_errors++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_errors);
+                       continue;
+               }
+ 
+@@ -1329,7 +1329,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       secy_stats->stats.InPktsUnknownSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
+               } else {
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+               }
+       }
+ 
+@@ -3438,7 +3438,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+ 
+       if (!secy->operational) {
+               kfree_skb(skb);
+-              dev->stats.tx_dropped++;
++              DEV_STATS_INC(dev, tx_dropped);
+               return NETDEV_TX_OK;
+       }
+ 
+@@ -3446,7 +3446,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+       skb = macsec_encrypt(skb, dev);
+       if (IS_ERR(skb)) {
+               if (PTR_ERR(skb) != -EINPROGRESS)
+-                      dev->stats.tx_dropped++;
++                      DEV_STATS_INC(dev, tx_dropped);
+               return NETDEV_TX_OK;
+       }
+ 
+@@ -3680,9 +3680,9 @@ static void macsec_get_stats64(struct net_device *dev,
+ 
+       dev_fetch_sw_netstats(s, dev->tstats);
+ 
+-      s->rx_dropped = dev->stats.rx_dropped;
+-      s->tx_dropped = dev->stats.tx_dropped;
+-      s->rx_errors = dev->stats.rx_errors;
++      s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped);
++      s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped);
++      s->rx_errors = atomic_long_read(&dev->stats.__rx_errors);
+ }
+ 
+ static int macsec_get_iflink(const struct net_device *dev)
+-- 
+2.40.1
+

diff --git a/queue-5.15/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch b/queue-5.15/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
new file mode 100644 (file)
index 0000000..baf52c4
--- /dev/null
+++ b/queue-5.15/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
@@ -0,0 +1,50 @@
+From b43a95ea187b9c986c5534c459f4c0789b40843e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 May 2023 13:11:47 +0100
+Subject: media: platform: mediatek: vpu: fix NULL ptr dereference
+
+From: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+
+[ Upstream commit 3df55cd773e8603b623425cc97b05e542854ad27 ]
+
+If pdev is NULL, then it is still dereferenced.
+
+This fixes this smatch warning:
+
+drivers/media/platform/mediatek/vpu/mtk_vpu.c:570 vpu_load_firmware() warn: address of NULL pointer 'pdev'
+
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Cc: Yunfei Dong <yunfei.dong@mediatek.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/platform/mtk-vpu/mtk_vpu.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c
+index 7f1647da0ade0..af59cc52fdd73 100644
+--- a/drivers/media/platform/mtk-vpu/mtk_vpu.c
++++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c
+@@ -562,15 +562,17 @@ static int load_requested_vpu(struct mtk_vpu *vpu,
+ int vpu_load_firmware(struct platform_device *pdev)
+ {
+       struct mtk_vpu *vpu;
+-      struct device *dev = &pdev->dev;
++      struct device *dev;
+       struct vpu_run *run;
+       int ret;
+ 
+       if (!pdev) {
+-              dev_err(dev, "VPU platform device is invalid\n");
++              pr_err("VPU platform device is invalid\n");
+               return -EINVAL;
+       }
+ 
++      dev = &pdev->dev;
++
+       vpu = platform_get_drvdata(pdev);
+       run = &vpu->run;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch b/queue-5.15/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
new file mode 100644 (file)
index 0000000..c3af169
--- /dev/null
+++ b/queue-5.15/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
@@ -0,0 +1,69 @@
+From 2fdc31c69f20301f64e011b505a59cd6067d02a3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Apr 2023 16:17:40 +0800
+Subject: media: v4l2-mem2mem: add lock to protect parameter num_rdy
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Yunfei Dong <yunfei.dong@mediatek.com>
+
+[ Upstream commit 56b5c3e67b0f9af3f45cf393be048ee8d8a92694 ]
+
+Getting below error when using KCSAN to check the driver. Adding lock to
+protect parameter num_rdy when getting the value with function:
+v4l2_m2m_num_src_bufs_ready/v4l2_m2m_num_dst_bufs_ready.
+
+kworker/u16:3: [name:report&]BUG: KCSAN: data-race in v4l2_m2m_buf_queue
+kworker/u16:3: [name:report&]
+
+kworker/u16:3: [name:report&]read-write to 0xffffff8105f35b94 of 1 bytes by task 20865 on cpu 7:
+kworker/u16:3:  v4l2_m2m_buf_queue+0xd8/0x10c
+
+Signed-off-by: Pina Chen <pina.chen@mediatek.com>
+Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/media/v4l2-mem2mem.h | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h
+index 5a91b548ecc0c..8d52c4506762d 100644
+--- a/include/media/v4l2-mem2mem.h
++++ b/include/media/v4l2-mem2mem.h
+@@ -588,7 +588,14 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx,
+ static inline
+ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ {
+-      return m2m_ctx->out_q_ctx.num_rdy;
++      unsigned int num_buf_rdy;
++      unsigned long flags;
++
++      spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags);
++      num_buf_rdy = m2m_ctx->out_q_ctx.num_rdy;
++      spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags);
++
++      return num_buf_rdy;
+ }
+ 
+ /**
+@@ -600,7 +607,14 @@ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ static inline
+ unsigned int v4l2_m2m_num_dst_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ {
+-      return m2m_ctx->cap_q_ctx.num_rdy;
++      unsigned int num_buf_rdy;
++      unsigned long flags;
++
++      spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags);
++      num_buf_rdy = m2m_ctx->cap_q_ctx.num_rdy;
++      spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags);
++
++      return num_buf_rdy;
+ }
+ 
+ /**
+-- 
+2.40.1
+

diff --git a/queue-5.15/mmc-bcm2835-fix-deferred-probing.patch b/queue-5.15/mmc-bcm2835-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..9f20819
--- /dev/null
+++ b/queue-5.15/mmc-bcm2835-fix-deferred-probing.patch
@@ -0,0 +1,44 @@
+From 836f38f0221e9d2129813e09200d66a4f3118926 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:11 +0300
+Subject: mmc: bcm2835: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit 71150ac12558bcd9d75e6e24cf7c872c2efd80f3 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 660fc733bd74 ("mmc: bcm2835: Add new driver for the sdhost controller.")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Link: https://lore.kernel.org/r/20230617203622.6812-2-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/bcm2835.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c
+index 8c2361e662774..985079943be76 100644
+--- a/drivers/mmc/host/bcm2835.c
++++ b/drivers/mmc/host/bcm2835.c
+@@ -1413,8 +1413,8 @@ static int bcm2835_probe(struct platform_device *pdev)
+       host->max_clk = clk_get_rate(clk);
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto err;
+       }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch b/queue-5.15/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
new file mode 100644 (file)
index 0000000..2965864
--- /dev/null
+++ b/queue-5.15/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
@@ -0,0 +1,155 @@
+From 69b272462ec1f14f1c510d3b0ca845b9a847d89a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Jun 2023 09:45:33 +0900
+Subject: mmc: sdhci-f-sdh30: Replace with sdhci_pltfm
+
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+[ Upstream commit 5def5c1c15bf22934ee227af85c1716762f3829f ]
+
+Even if sdhci_pltfm_pmops is specified for PM, this driver doesn't apply
+sdhci_pltfm, so the structure is not correctly referenced in PM functions.
+This applies sdhci_pltfm to this driver to fix this issue.
+
+- Call sdhci_pltfm_init() instead of sdhci_alloc_host() and
+  other functions that covered by sdhci_pltfm.
+- Move ops and quirks to sdhci_pltfm_data
+- Replace sdhci_priv() with own private function sdhci_f_sdh30_priv().
+
+Fixes: 87a507459f49 ("mmc: sdhci: host: add new f_sdh30")
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20230630004533.26644-1-hayashi.kunihiko@socionext.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci_f_sdh30.c | 60 ++++++++++++++------------------
+ 1 file changed, 27 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c
+index 6c4f43e112826..8876fd1c7eee0 100644
+--- a/drivers/mmc/host/sdhci_f_sdh30.c
++++ b/drivers/mmc/host/sdhci_f_sdh30.c
+@@ -26,9 +26,16 @@ struct f_sdhost_priv {
+       bool enable_cmd_dat_delay;
+ };
+ 
++static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
++{
++      struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++
++      return sdhci_pltfm_priv(pltfm_host);
++}
++
+ static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
+ {
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+       u32 ctrl = 0;
+ 
+       usleep_range(2500, 3000);
+@@ -61,7 +68,7 @@ static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
+ 
+ static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
+ {
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+       u32 ctl;
+ 
+       if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
+@@ -85,30 +92,32 @@ static const struct sdhci_ops sdhci_f_sdh30_ops = {
+       .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+ 
++static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
++      .ops = &sdhci_f_sdh30_ops,
++      .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
++              | SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
++      .quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
++              |  SDHCI_QUIRK2_TUNING_WORK_AROUND,
++};
++
+ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+ {
+       struct sdhci_host *host;
+       struct device *dev = &pdev->dev;
+-      int irq, ctrl = 0, ret = 0;
++      int ctrl = 0, ret = 0;
+       struct f_sdhost_priv *priv;
++      struct sdhci_pltfm_host *pltfm_host;
+       u32 reg = 0;
+ 
+-      irq = platform_get_irq(pdev, 0);
+-      if (irq < 0)
+-              return irq;
+-
+-      host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
++      host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
++                              sizeof(struct f_sdhost_priv));
+       if (IS_ERR(host))
+               return PTR_ERR(host);
+ 
+-      priv = sdhci_priv(host);
++      pltfm_host = sdhci_priv(host);
++      priv = sdhci_pltfm_priv(pltfm_host);
+       priv->dev = dev;
+ 
+-      host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+-                     SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+-      host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
+-                      SDHCI_QUIRK2_TUNING_WORK_AROUND;
+-
+       priv->enable_cmd_dat_delay = device_property_read_bool(dev,
+                                               "fujitsu,cmd-dat-delay-select");
+ 
+@@ -116,18 +125,6 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+       if (ret)
+               goto err;
+ 
+-      platform_set_drvdata(pdev, host);
+-
+-      host->hw_name = "f_sdh30";
+-      host->ops = &sdhci_f_sdh30_ops;
+-      host->irq = irq;
+-
+-      host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
+-      if (IS_ERR(host->ioaddr)) {
+-              ret = PTR_ERR(host->ioaddr);
+-              goto err;
+-      }
+-
+       if (dev_of_node(dev)) {
+               sdhci_get_of_property(pdev);
+ 
+@@ -182,23 +179,20 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+ err_clk:
+       clk_disable_unprepare(priv->clk_iface);
+ err:
+-      sdhci_free_host(host);
++      sdhci_pltfm_free(pdev);
++
+       return ret;
+ }
+ 
+ static int sdhci_f_sdh30_remove(struct platform_device *pdev)
+ {
+       struct sdhci_host *host = platform_get_drvdata(pdev);
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
+-
+-      sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
+-                        0xffffffff);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+ 
+       clk_disable_unprepare(priv->clk_iface);
+       clk_disable_unprepare(priv->clk);
+ 
+-      sdhci_free_host(host);
+-      platform_set_drvdata(pdev, NULL);
++      sdhci_pltfm_unregister(pdev);
+ 
+       return 0;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/mmc-sdhci-spear-fix-deferred-probing.patch b/queue-5.15/mmc-sdhci-spear-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..3e5c508
--- /dev/null
+++ b/queue-5.15/mmc-sdhci-spear-fix-deferred-probing.patch
@@ -0,0 +1,46 @@
+From 06fb398c032bd2317c2f2fdffd455c3e052265ca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:19 +0300
+Subject: mmc: sdhci-spear: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit 8d0caeedcd05a721f3cc2537b0ea212ec4027307 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 682798a596a6 ("mmc: sdhci-spear: Handle return value of platform_get_irq")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20230617203622.6812-10-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-spear.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci-spear.c b/drivers/mmc/host/sdhci-spear.c
+index d463e2fd5b1a8..c79035727b20b 100644
+--- a/drivers/mmc/host/sdhci-spear.c
++++ b/drivers/mmc/host/sdhci-spear.c
+@@ -65,8 +65,8 @@ static int sdhci_probe(struct platform_device *pdev)
+       host->hw_name = "sdhci";
+       host->ops = &sdhci_pltfm_ops;
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto err_host;
+       }
+       host->quirks = SDHCI_QUIRK_BROKEN_ADMA;
+-- 
+2.40.1
+

diff --git a/queue-5.15/mmc-sunxi-fix-deferred-probing.patch b/queue-5.15/mmc-sunxi-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..2f8a974
--- /dev/null
+++ b/queue-5.15/mmc-sunxi-fix-deferred-probing.patch
@@ -0,0 +1,45 @@
+From 724c4ab36a66696dee722686cc2b91819a3dd18b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:21 +0300
+Subject: mmc: sunxi: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit c2df53c5806cfd746dae08e07bc8c4ad247c3b70 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 2408a08583d2 ("mmc: sunxi-mmc: Handle return value of platform_get_irq")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20230617203622.6812-12-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sunxi-mmc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 032f2c03e8fb0..3c213816db786 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1341,8 +1341,8 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
+               return ret;
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto error_disable_mmc;
+       }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch b/queue-5.15/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch
new file mode 100644 (file)
index 0000000..db613e2
--- /dev/null
+++ b/queue-5.15/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch
@@ -0,0 +1,55 @@
+From 391c70070422467c722f1ebafe2c9740c9c75143 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 18:17:42 +0300
+Subject: net/ncsi: change from ndo_set_mac_address to dev_set_mac_address
+
+From: Ivan Mikhaylov <fr0st61te@gmail.com>
+
+[ Upstream commit 790071347a0a1a89e618eedcd51c687ea783aeb3 ]
+
+Change ndo_set_mac_address to dev_set_mac_address because
+dev_set_mac_address provides a way to notify network layer about MAC
+change. In other case, services may not aware about MAC change and keep
+using old one which set from network adapter driver.
+
+As example, DHCP client from systemd do not update MAC address without
+notification from net subsystem which leads to the problem with acquiring
+the right address from DHCP server.
+
+Fixes: cb10c7c0dfd9e ("net/ncsi: Add NCSI Broadcom OEM command")
+Cc: stable@vger.kernel.org # v6.0+ 2f38e84 net/ncsi: make one oem_gma function for all mfr id
+Signed-off-by: Paul Fertser <fercerpav@gmail.com>
+Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/ncsi/ncsi-rsp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/net/ncsi/ncsi-rsp.c b/net/ncsi/ncsi-rsp.c
+index 6447a09932f55..df548e781aab0 100644
+--- a/net/ncsi/ncsi-rsp.c
++++ b/net/ncsi/ncsi-rsp.c
+@@ -616,7 +616,6 @@ static int ncsi_rsp_handler_oem_mlx_gma(struct ncsi_request *nr)
+ {
+       struct ncsi_dev_priv *ndp = nr->ndp;
+       struct net_device *ndev = ndp->ndev.dev;
+-      const struct net_device_ops *ops = ndev->netdev_ops;
+       struct ncsi_rsp_oem_pkt *rsp;
+       struct sockaddr saddr;
+       int ret = 0;
+@@ -630,7 +629,9 @@ static int ncsi_rsp_handler_oem_mlx_gma(struct ncsi_request *nr)
+       /* Set the flag for GMA command which should only be called once */
+       ndp->gma_flag = 1;
+ 
+-      ret = ops->ndo_set_mac_address(ndev, &saddr);
++      rtnl_lock();
++      ret = dev_set_mac_address(ndev, &saddr, NULL);
++      rtnl_unlock();
+       if (ret < 0)
+               netdev_warn(ndev, "NCSI: 'Writing mac address to device failed\n");
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/net-tls-avoid-discarding-data-on-record-close.patch b/queue-5.15/net-tls-avoid-discarding-data-on-record-close.patch
new file mode 100644 (file)
index 0000000..32f0f20
--- /dev/null
+++ b/queue-5.15/net-tls-avoid-discarding-data-on-record-close.patch
@@ -0,0 +1,166 @@
+From 4b4a2d125afbb5db5eb5a75787d94d9292e9c4cc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 4 Aug 2023 15:59:51 -0700
+Subject: net: tls: avoid discarding data on record close
+
+From: Jakub Kicinski <kuba@kernel.org>
+
+[ Upstream commit 6b47808f223c70ff564f9b363446d2a5fa1e05b2 ]
+
+TLS records end with a 16B tag. For TLS device offload we only
+need to make space for this tag in the stream, the device will
+generate and replace it with the actual calculated tag.
+
+Long time ago the code would just re-reference the head frag
+which mostly worked but was suboptimal because it prevented TCP
+from combining the record into a single skb frag. I'm not sure
+if it was correct as the first frag may be shorter than the tag.
+
+The commit under fixes tried to replace that with using the page
+frag and if the allocation failed rolling back the data, if record
+was long enough. It achieves better fragment coalescing but is
+also buggy.
+
+We don't roll back the iterator, so unless we're at the end of
+send we'll skip the data we designated as tag and start the
+next record as if the rollback never happened.
+There's also the possibility that the record was constructed
+with MSG_MORE and the data came from a different syscall and
+we already told the user space that we "got it".
+
+Allocate a single dummy page and use it as fallback.
+
+Found by code inspection, and proven by forcing allocation
+failures.
+
+Fixes: e7b159a48ba6 ("net/tls: remove the record tail optimization")
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/tls/tls_device.c | 64 +++++++++++++++++++++++---------------------
+ 1 file changed, 33 insertions(+), 31 deletions(-)
+
+diff --git a/net/tls/tls_device.c b/net/tls/tls_device.c
+index 8012bd86437c9..88785196a8966 100644
+--- a/net/tls/tls_device.c
++++ b/net/tls/tls_device.c
+@@ -51,6 +51,8 @@ static LIST_HEAD(tls_device_list);
+ static LIST_HEAD(tls_device_down_list);
+ static DEFINE_SPINLOCK(tls_device_lock);
+ 
++static struct page *dummy_page;
++
+ static void tls_device_free_ctx(struct tls_context *ctx)
+ {
+       if (ctx->tx_conf == TLS_HW) {
+@@ -297,36 +299,33 @@ static int tls_push_record(struct sock *sk,
+       return tls_push_sg(sk, ctx, offload_ctx->sg_tx_data, 0, flags);
+ }
+ 
+-static int tls_device_record_close(struct sock *sk,
+-                                 struct tls_context *ctx,
+-                                 struct tls_record_info *record,
+-                                 struct page_frag *pfrag,
+-                                 unsigned char record_type)
++static void tls_device_record_close(struct sock *sk,
++                                  struct tls_context *ctx,
++                                  struct tls_record_info *record,
++                                  struct page_frag *pfrag,
++                                  unsigned char record_type)
+ {
+       struct tls_prot_info *prot = &ctx->prot_info;
+-      int ret;
++      struct page_frag dummy_tag_frag;
+ 
+       /* append tag
+        * device will fill in the tag, we just need to append a placeholder
+        * use socket memory to improve coalescing (re-using a single buffer
+        * increases frag count)
+-       * if we can't allocate memory now, steal some back from data
++       * if we can't allocate memory now use the dummy page
+        */
+-      if (likely(skb_page_frag_refill(prot->tag_size, pfrag,
+-                                      sk->sk_allocation))) {
+-              ret = 0;
+-              tls_append_frag(record, pfrag, prot->tag_size);
+-      } else {
+-              ret = prot->tag_size;
+-              if (record->len <= prot->overhead_size)
+-                      return -ENOMEM;
++      if (unlikely(pfrag->size - pfrag->offset < prot->tag_size) &&
++          !skb_page_frag_refill(prot->tag_size, pfrag, sk->sk_allocation)) {
++              dummy_tag_frag.page = dummy_page;
++              dummy_tag_frag.offset = 0;
++              pfrag = &dummy_tag_frag;
+       }
++      tls_append_frag(record, pfrag, prot->tag_size);
+ 
+       /* fill prepend */
+       tls_fill_prepend(ctx, skb_frag_address(&record->frags[0]),
+                        record->len - prot->overhead_size,
+                        record_type);
+-      return ret;
+ }
+ 
+ static int tls_create_new_record(struct tls_offload_context_tx *offload_ctx,
+@@ -502,18 +501,8 @@ static int tls_push_data(struct sock *sk,
+ 
+               if (done || record->len >= max_open_record_len ||
+                   (record->num_frags >= MAX_SKB_FRAGS - 1)) {
+-                      rc = tls_device_record_close(sk, tls_ctx, record,
+-                                                   pfrag, record_type);
+-                      if (rc) {
+-                              if (rc > 0) {
+-                                      size += rc;
+-                              } else {
+-                                      size = orig_size;
+-                                      destroy_record(record);
+-                                      ctx->open_record = NULL;
+-                                      break;
+-                              }
+-                      }
++                      tls_device_record_close(sk, tls_ctx, record,
++                                              pfrag, record_type);
+ 
+                       rc = tls_push_record(sk,
+                                            tls_ctx,
+@@ -1403,14 +1392,26 @@ int __init tls_device_init(void)
+ {
+       int err;
+ 
+-      destruct_wq = alloc_workqueue("ktls_device_destruct", 0, 0);
+-      if (!destruct_wq)
++      dummy_page = alloc_page(GFP_KERNEL);
++      if (!dummy_page)
+               return -ENOMEM;
+ 
++      destruct_wq = alloc_workqueue("ktls_device_destruct", 0, 0);
++      if (!destruct_wq) {
++              err = -ENOMEM;
++              goto err_free_dummy;
++      }
++
+       err = register_netdevice_notifier(&tls_dev_notifier);
+       if (err)
+-              destroy_workqueue(destruct_wq);
++              goto err_destroy_wq;
+ 
++      return 0;
++
++err_destroy_wq:
++      destroy_workqueue(destruct_wq);
++err_free_dummy:
++      put_page(dummy_page);
+       return err;
+ }
+ 
+@@ -1420,4 +1421,5 @@ void __exit tls_device_cleanup(void)
+       flush_workqueue(destruct_wq);
+       destroy_workqueue(destruct_wq);
+       clean_acked_data_flush();
++      put_page(dummy_page);
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/net-tls-multi-threaded-calls-to-tx-tls_dev_del.patch b/queue-5.15/net-tls-multi-threaded-calls-to-tx-tls_dev_del.patch
new file mode 100644 (file)
index 0000000..d8b248a
--- /dev/null
+++ b/queue-5.15/net-tls-multi-threaded-calls-to-tx-tls_dev_del.patch
@@ -0,0 +1,174 @@
+From 1229b99a1d124089e69c5c8aad812bb0ebbc4f74 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 12:43:42 +0300
+Subject: net/tls: Multi-threaded calls to TX tls_dev_del
+
+From: Tariq Toukan <tariqt@nvidia.com>
+
+[ Upstream commit 7adc91e0c93901a0eeeea10665d0feb48ffde2d4 ]
+
+Multiple TLS device-offloaded contexts can be added in parallel via
+concurrent calls to .tls_dev_add, while calls to .tls_dev_del are
+sequential in tls_device_gc_task.
+
+This is not a sustainable behavior. This creates a rate gap between add
+and del operations (addition rate outperforms the deletion rate).  When
+running for enough time, the TLS device resources could get exhausted,
+failing to offload new connections.
+
+Replace the single-threaded garbage collector work with a per-context
+alternative, so they can be handled on several cores in parallel. Use
+a new dedicated destruct workqueue for this.
+
+Tested with mlx5 device:
+Before: 22141 add/sec,   103 del/sec
+After:  11684 add/sec, 11684 del/sec
+
+Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
+Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com>
+Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: 6b47808f223c ("net: tls: avoid discarding data on record close")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/net/tls.h    |  2 ++
+ net/tls/tls_device.c | 63 ++++++++++++++++++++++----------------------
+ 2 files changed, 33 insertions(+), 32 deletions(-)
+
+diff --git a/include/net/tls.h b/include/net/tls.h
+index bf3d63a527885..eda0015c5c592 100644
+--- a/include/net/tls.h
++++ b/include/net/tls.h
+@@ -179,6 +179,8 @@ struct tls_offload_context_tx {
+ 
+       struct scatterlist sg_tx_data[MAX_SKB_FRAGS];
+       void (*sk_destruct)(struct sock *sk);
++      struct work_struct destruct_work;
++      struct tls_context *ctx;
+       u8 driver_state[] __aligned(8);
+       /* The TLS layer reserves room for driver specific state
+        * Currently the belief is that there is not enough
+diff --git a/net/tls/tls_device.c b/net/tls/tls_device.c
+index 19ba57245777b..8012bd86437c9 100644
+--- a/net/tls/tls_device.c
++++ b/net/tls/tls_device.c
+@@ -45,10 +45,8 @@
+  */
+ static DECLARE_RWSEM(device_offload_lock);
+ 
+-static void tls_device_gc_task(struct work_struct *work);
++static struct workqueue_struct *destruct_wq __read_mostly;
+ 
+-static DECLARE_WORK(tls_device_gc_work, tls_device_gc_task);
+-static LIST_HEAD(tls_device_gc_list);
+ static LIST_HEAD(tls_device_list);
+ static LIST_HEAD(tls_device_down_list);
+ static DEFINE_SPINLOCK(tls_device_lock);
+@@ -67,29 +65,17 @@ static void tls_device_free_ctx(struct tls_context *ctx)
+       tls_ctx_free(NULL, ctx);
+ }
+ 
+-static void tls_device_gc_task(struct work_struct *work)
++static void tls_device_tx_del_task(struct work_struct *work)
+ {
+-      struct tls_context *ctx, *tmp;
+-      unsigned long flags;
+-      LIST_HEAD(gc_list);
+-
+-      spin_lock_irqsave(&tls_device_lock, flags);
+-      list_splice_init(&tls_device_gc_list, &gc_list);
+-      spin_unlock_irqrestore(&tls_device_lock, flags);
+-
+-      list_for_each_entry_safe(ctx, tmp, &gc_list, list) {
+-              struct net_device *netdev = ctx->netdev;
++      struct tls_offload_context_tx *offload_ctx =
++              container_of(work, struct tls_offload_context_tx, destruct_work);
++      struct tls_context *ctx = offload_ctx->ctx;
++      struct net_device *netdev = ctx->netdev;
+ 
+-              if (netdev && ctx->tx_conf == TLS_HW) {
+-                      netdev->tlsdev_ops->tls_dev_del(netdev, ctx,
+-                                                      TLS_OFFLOAD_CTX_DIR_TX);
+-                      dev_put(netdev);
+-                      ctx->netdev = NULL;
+-              }
+-
+-              list_del(&ctx->list);
+-              tls_device_free_ctx(ctx);
+-      }
++      netdev->tlsdev_ops->tls_dev_del(netdev, ctx, TLS_OFFLOAD_CTX_DIR_TX);
++      dev_put(netdev);
++      ctx->netdev = NULL;
++      tls_device_free_ctx(ctx);
+ }
+ 
+ static void tls_device_queue_ctx_destruction(struct tls_context *ctx)
+@@ -103,16 +89,15 @@ static void tls_device_queue_ctx_destruction(struct tls_context *ctx)
+               return;
+       }
+ 
++      list_del(&ctx->list); /* Remove from tls_device_list / tls_device_down_list */
+       async_cleanup = ctx->netdev && ctx->tx_conf == TLS_HW;
+       if (async_cleanup) {
+-              list_move_tail(&ctx->list, &tls_device_gc_list);
++              struct tls_offload_context_tx *offload_ctx = tls_offload_ctx_tx(ctx);
+ 
+-              /* schedule_work inside the spinlock
++              /* queue_work inside the spinlock
+                * to make sure tls_device_down waits for that work.
+                */
+-              schedule_work(&tls_device_gc_work);
+-      } else {
+-              list_del(&ctx->list);
++              queue_work(destruct_wq, &offload_ctx->destruct_work);
+       }
+       spin_unlock_irqrestore(&tls_device_lock, flags);
+ 
+@@ -1115,6 +1100,9 @@ int tls_set_device_offload(struct sock *sk, struct tls_context *ctx)
+       start_marker_record->len = 0;
+       start_marker_record->num_frags = 0;
+ 
++      INIT_WORK(&offload_ctx->destruct_work, tls_device_tx_del_task);
++      offload_ctx->ctx = ctx;
++
+       INIT_LIST_HEAD(&offload_ctx->records_list);
+       list_add_tail(&start_marker_record->list, &offload_ctx->records_list);
+       spin_lock_init(&offload_ctx->lock);
+@@ -1372,7 +1360,7 @@ static int tls_device_down(struct net_device *netdev)
+ 
+       up_write(&device_offload_lock);
+ 
+-      flush_work(&tls_device_gc_work);
++      flush_workqueue(destruct_wq);
+ 
+       return NOTIFY_DONE;
+ }
+@@ -1413,12 +1401,23 @@ static struct notifier_block tls_dev_notifier = {
+ 
+ int __init tls_device_init(void)
+ {
+-      return register_netdevice_notifier(&tls_dev_notifier);
++      int err;
++
++      destruct_wq = alloc_workqueue("ktls_device_destruct", 0, 0);
++      if (!destruct_wq)
++              return -ENOMEM;
++
++      err = register_netdevice_notifier(&tls_dev_notifier);
++      if (err)
++              destroy_workqueue(destruct_wq);
++
++      return err;
+ }
+ 
+ void __exit tls_device_cleanup(void)
+ {
+       unregister_netdevice_notifier(&tls_dev_notifier);
+-      flush_work(&tls_device_gc_work);
++      flush_workqueue(destruct_wq);
++      destroy_workqueue(destruct_wq);
+       clean_acked_data_flush();
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/net-tls-perform-immediate-device-ctx-cleanup-when-po.patch b/queue-5.15/net-tls-perform-immediate-device-ctx-cleanup-when-po.patch
new file mode 100644 (file)
index 0000000..c106113
--- /dev/null
+++ b/queue-5.15/net-tls-perform-immediate-device-ctx-cleanup-when-po.patch
@@ -0,0 +1,72 @@
+From ad9b0cff3eb47ef9cb9b956de7aa6fdc0a686eb3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 12:43:41 +0300
+Subject: net/tls: Perform immediate device ctx cleanup when possible
+
+From: Tariq Toukan <tariqt@nvidia.com>
+
+[ Upstream commit 113671b255ee3b9f5585a6d496ef0e675e698698 ]
+
+TLS context destructor can be run in atomic context. Cleanup operations
+for device-offloaded contexts could require access and interaction with
+the device callbacks, which might sleep. Hence, the cleanup of such
+contexts must be deferred and completed inside an async work.
+
+For all others, this is not necessary, as cleanup is atomic. Invoke
+cleanup immediately for them, avoiding queueing redundant gc work.
+
+Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
+Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com>
+Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: 6b47808f223c ("net: tls: avoid discarding data on record close")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/tls/tls_device.c | 26 ++++++++++++++++++--------
+ 1 file changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/net/tls/tls_device.c b/net/tls/tls_device.c
+index cf75969375cfa..19ba57245777b 100644
+--- a/net/tls/tls_device.c
++++ b/net/tls/tls_device.c
+@@ -95,19 +95,29 @@ static void tls_device_gc_task(struct work_struct *work)
+ static void tls_device_queue_ctx_destruction(struct tls_context *ctx)
+ {
+       unsigned long flags;
++      bool async_cleanup;
+ 
+       spin_lock_irqsave(&tls_device_lock, flags);
+-      if (unlikely(!refcount_dec_and_test(&ctx->refcount)))
+-              goto unlock;
++      if (unlikely(!refcount_dec_and_test(&ctx->refcount))) {
++              spin_unlock_irqrestore(&tls_device_lock, flags);
++              return;
++      }
+ 
+-      list_move_tail(&ctx->list, &tls_device_gc_list);
++      async_cleanup = ctx->netdev && ctx->tx_conf == TLS_HW;
++      if (async_cleanup) {
++              list_move_tail(&ctx->list, &tls_device_gc_list);
+ 
+-      /* schedule_work inside the spinlock
+-       * to make sure tls_device_down waits for that work.
+-       */
+-      schedule_work(&tls_device_gc_work);
+-unlock:
++              /* schedule_work inside the spinlock
++               * to make sure tls_device_down waits for that work.
++               */
++              schedule_work(&tls_device_gc_work);
++      } else {
++              list_del(&ctx->list);
++      }
+       spin_unlock_irqrestore(&tls_device_lock, flags);
++
++      if (!async_cleanup)
++              tls_device_free_ctx(ctx);
+ }
+ 
+ /* We assume that the socket is already connected */
+-- 
+2.40.1
+

diff --git a/queue-5.15/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch b/queue-5.15/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
new file mode 100644 (file)
index 0000000..6a16295
--- /dev/null
+++ b/queue-5.15/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
@@ -0,0 +1,61 @@
+From 26bf0503e78fceb46d0d9ef8270ba2a77e945053 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Jun 2023 10:13:37 +0200
+Subject: ovl: check type and offset of struct vfsmount in ovl_entry
+
+From: Christian Brauner <brauner@kernel.org>
+
+[ Upstream commit f723edb8a532cd26e1ff0a2b271d73762d48f762 ]
+
+Porting overlayfs to the new amount api I started experiencing random
+crashes that couldn't be explained easily. So after much debugging and
+reasoning it became clear that struct ovl_entry requires the point to
+struct vfsmount to be the first member and of type struct vfsmount.
+
+During the port I added a new member at the beginning of struct
+ovl_entry which broke all over the place in the form of random crashes
+and cache corruptions. While there's a comment in ovl_free_fs() to the
+effect of "Hack! Reuse ofs->layers as a vfsmount array before freeing
+it" there's no such comment on struct ovl_entry which makes this easy to
+trip over.
+
+Add a comment and two static asserts for both the offset and the type of
+pointer in struct ovl_entry.
+
+Signed-off-by: Christian Brauner <brauner@kernel.org>
+Signed-off-by: Amir Goldstein <amir73il@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/overlayfs/ovl_entry.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/fs/overlayfs/ovl_entry.h b/fs/overlayfs/ovl_entry.h
+index b2d64f3c974bb..08031638bbeec 100644
+--- a/fs/overlayfs/ovl_entry.h
++++ b/fs/overlayfs/ovl_entry.h
+@@ -32,6 +32,7 @@ struct ovl_sb {
+ };
+ 
+ struct ovl_layer {
++      /* ovl_free_fs() relies on @mnt being the first member! */
+       struct vfsmount *mnt;
+       /* Trap in ovl inode cache */
+       struct inode *trap;
+@@ -42,6 +43,14 @@ struct ovl_layer {
+       int fsid;
+ };
+ 
++/*
++ * ovl_free_fs() relies on @mnt being the first member when unmounting
++ * the private mounts created for each layer. Let's check both the
++ * offset and type.
++ */
++static_assert(offsetof(struct ovl_layer, mnt) == 0);
++static_assert(__same_type(typeof_member(struct ovl_layer, mnt), struct vfsmount *));
++
+ struct ovl_path {
+       const struct ovl_layer *layer;
+       struct dentry *dentry;
+-- 
+2.40.1
+

diff --git a/queue-5.15/pci-tegra194-fix-possible-array-out-of-bounds-access.patch b/queue-5.15/pci-tegra194-fix-possible-array-out-of-bounds-access.patch
new file mode 100644 (file)
index 0000000..ece2bfc
--- /dev/null
+++ b/queue-5.15/pci-tegra194-fix-possible-array-out-of-bounds-access.patch
@@ -0,0 +1,66 @@
+From d181302accaee10b863ebe6ed6fc468aa08d05d9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 May 2023 23:02:09 +0530
+Subject: PCI: tegra194: Fix possible array out of bounds access
+
+From: Sumit Gupta <sumitg@nvidia.com>
+
+[ Upstream commit 205b3d02d57ce6dce96f6d2b9c230f56a9bf9817 ]
+
+Add check to fix the possible array out of bounds violation by
+making speed equal to GEN1_CORE_CLK_FREQ when its value is more
+than the size of "pcie_gen_freq" array. This array has size of
+four but possible speed (CLS) values are from "0 to 0xF". So,
+"speed - 1" values are "-1 to 0xE".
+
+Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
+Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
+Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/
+Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
+index bdd84765e6460..765abe0732282 100644
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -239,6 +239,7 @@
+ #define EP_STATE_ENABLED      1
+ 
+ static const unsigned int pcie_gen_freq[] = {
++      GEN1_CORE_CLK_FREQ,     /* PCI_EXP_LNKSTA_CLS == 0; undefined */
+       GEN1_CORE_CLK_FREQ,
+       GEN2_CORE_CLK_FREQ,
+       GEN3_CORE_CLK_FREQ,
+@@ -452,7 +453,11 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
+ 
+       speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
+               PCI_EXP_LNKSTA_CLS;
+-      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
++
++      if (speed >= ARRAY_SIZE(pcie_gen_freq))
++              speed = 0;
++
++      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
+ 
+       /* If EP doesn't advertise L1SS, just return */
+       val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
+@@ -989,7 +994,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
+ 
+       speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
+               PCI_EXP_LNKSTA_CLS;
+-      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
++
++      if (speed >= ARRAY_SIZE(pcie_gen_freq))
++              speed = 0;
++
++      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
+ 
+       tegra_pcie_enable_interrupts(pp);
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch b/queue-5.15/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
new file mode 100644 (file)
index 0000000..2c68de5
--- /dev/null
+++ b/queue-5.15/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
@@ -0,0 +1,66 @@
+From 7298ccfef8909bf9d24a8bfba3d8b09ab70023b4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 May 2023 20:45:29 +0200
+Subject: pcmcia: rsrc_nonstatic: Fix memory leak in
+ nonstatic_release_resource_db()
+
+From: Armin Wolf <W_Armin@gmx.de>
+
+[ Upstream commit c85fd9422fe0f5d667305efb27f56d09eab120b0 ]
+
+When nonstatic_release_resource_db() frees all resources associated
+with an PCMCIA socket, it forgets to free socket_data too, causing
+a memory leak observable with kmemleak:
+
+unreferenced object 0xc28d1000 (size 64):
+  comm "systemd-udevd", pid 297, jiffies 4294898478 (age 194.484s)
+  hex dump (first 32 bytes):
+    00 00 00 00 00 00 00 00 f0 85 0e c3 00 00 00 00  ................
+    00 00 00 00 0c 10 8d c2 00 00 00 00 00 00 00 00  ................
+  backtrace:
+    [<ffda4245>] __kmem_cache_alloc_node+0x2d7/0x4a0
+    [<7e51f0c8>] kmalloc_trace+0x31/0xa4
+    [<d52b4ca0>] nonstatic_init+0x24/0x1a4 [pcmcia_rsrc]
+    [<a2f13e08>] pcmcia_register_socket+0x200/0x35c [pcmcia_core]
+    [<a728be1b>] yenta_probe+0x4d8/0xa70 [yenta_socket]
+    [<c48fac39>] pci_device_probe+0x99/0x194
+    [<84b7c690>] really_probe+0x181/0x45c
+    [<8060fe6e>] __driver_probe_device+0x75/0x1f4
+    [<b9b76f43>] driver_probe_device+0x28/0xac
+    [<648b766f>] __driver_attach+0xeb/0x1e4
+    [<6e9659eb>] bus_for_each_dev+0x61/0xb4
+    [<25a669f3>] driver_attach+0x1e/0x28
+    [<d8671d6b>] bus_add_driver+0x102/0x20c
+    [<df0d323c>] driver_register+0x5b/0x120
+    [<942cd8a4>] __pci_register_driver+0x44/0x4c
+    [<e536027e>] __UNIQUE_ID___addressable_cleanup_module188+0x1c/0xfffff000 [iTCO_vendor_support]
+
+Fix this by freeing socket_data too.
+
+Tested on a Acer Travelmate 4002WLMi by manually binding/unbinding
+the yenta_cardbus driver (yenta_socket).
+
+Signed-off-by: Armin Wolf <W_Armin@gmx.de>
+Message-ID: <20230512184529.5094-1-W_Armin@gmx.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pcmcia/rsrc_nonstatic.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c
+index 1cac528707111..e6c90c0bb7646 100644
+--- a/drivers/pcmcia/rsrc_nonstatic.c
++++ b/drivers/pcmcia/rsrc_nonstatic.c
+@@ -1053,6 +1053,8 @@ static void nonstatic_release_resource_db(struct pcmcia_socket *s)
+               q = p->next;
+               kfree(p);
+       }
++
++      kfree(data);
+ }
+ 
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/phy-qcom-qmp-combo-fix-init-count-imbalance.patch b/queue-5.15/phy-qcom-qmp-combo-fix-init-count-imbalance.patch
new file mode 100644 (file)
index 0000000..740e0e6
--- /dev/null
+++ b/queue-5.15/phy-qcom-qmp-combo-fix-init-count-imbalance.patch
@@ -0,0 +1,53 @@
+From 64a74af20c447e82aa79161d831c99d7fc1fa71e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 May 2023 12:38:09 +0200
+Subject: phy: qcom-qmp-combo: fix init-count imbalance
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 9bf03a0cbd80a256bc1e1c4bcc80bc2b06b8b2b9 ]
+
+The init counter is not decremented on initialisation errors, which
+prevents retrying initialisation and can lead to the runtime suspend
+callback attempting to disable resources that have never been enabled.
+
+Add the missing decrement on initialisation errors so that the counter
+reflects the state of the device.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Cc: stable@vger.kernel.org     # 4.12
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20230502103810.12061-2-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+index c7309e981bfb5..96282a118e635 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -5085,7 +5085,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+       ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
+       if (ret) {
+               dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
+-              goto err_unlock;
++              goto err_decrement_count;
+       }
+ 
+       for (i = 0; i < cfg->num_resets; i++) {
+@@ -5155,7 +5155,8 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+               reset_control_assert(qmp->resets[i]);
+ err_disable_regulators:
+       regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
+-err_unlock:
++err_decrement_count:
++      qmp->init_count--;
+       mutex_unlock(&qmp->phy_mutex);
+ 
+       return ret;
+-- 
+2.40.1
+

diff --git a/queue-5.15/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch b/queue-5.15/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
new file mode 100644 (file)
index 0000000..b38f8a2
--- /dev/null
+++ b/queue-5.15/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
@@ -0,0 +1,31819 @@
+From a2a081521fdb60da1ac3e58e184059d206684607 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:35:32 +0300
+Subject: phy: qcom-qmp: create copies of QMP PHY driver
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
+
+In order to split and cleanup the single monstrous QMP PHY driver,
+create blind copies of the current file. They will be used for:
+- PCIe (and a separate msm8996 PCIe PHY driver)
+- UFS
+- USB
+- Combo DP + USB
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 9bf03a0cbd80 ("phy: qcom-qmp-combo: fix init-count imbalance")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c     | 6350 +++++++++++++++++
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c  | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c       | 6350 +++++++++++++++++
+ 5 files changed, 31750 insertions(+)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+-- 
+2.40.1
+

diff --git a/queue-5.15/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch b/queue-5.15/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
new file mode 100644 (file)
index 0000000..f970948
--- /dev/null
+++ b/queue-5.15/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
@@ -0,0 +1,52 @@
+From 88bff3133ce610f1604cc32c1881d36b1e74363a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 May 2023 12:38:10 +0200
+Subject: phy: qcom-qmp-pcie-msm8996: fix init-count imbalance
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit e42f110700ed7293700c26145e1ed07ea05ac3f6 ]
+
+The init counter is not decremented on initialisation errors, which
+prevents retrying initialisation.
+
+Add the missing decrement on initialisation errors so that the counter
+reflects the state of the device.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Cc: stable@vger.kernel.org      # 4.12
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20230502103810.12061-3-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index c7309e981bfb5..96282a118e635 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -5085,7 +5085,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+       ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
+       if (ret) {
+               dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
+-              goto err_unlock;
++              goto err_decrement_count;
+       }
+ 
+       for (i = 0; i < cfg->num_resets; i++) {
+@@ -5155,7 +5155,8 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+               reset_control_assert(qmp->resets[i]);
+ err_disable_regulators:
+       regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
+-err_unlock:
++err_decrement_count:
++      qmp->init_count--;
+       mutex_unlock(&qmp->phy_mutex);
+ 
+       return ret;
+-- 
+2.40.1
+

diff --git a/queue-5.15/powerpc-kasan-disable-kcov-in-kasan-code.patch b/queue-5.15/powerpc-kasan-disable-kcov-in-kasan-code.patch
new file mode 100644 (file)
index 0000000..c546d4d
--- /dev/null
+++ b/queue-5.15/powerpc-kasan-disable-kcov-in-kasan-code.patch
@@ -0,0 +1,40 @@
+From 2fb02896297baae1985dd2fa219fd66de7477992 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 10 Jul 2023 14:41:43 +1000
+Subject: powerpc/kasan: Disable KCOV in KASAN code
+
+From: Benjamin Gray <bgray@linux.ibm.com>
+
+[ Upstream commit ccb381e1af1ace292153c88eb1fffa5683d16a20 ]
+
+As per the generic KASAN code in mm/kasan, disable KCOV with
+KCOV_INSTRUMENT := n in the makefile.
+
+This fixes a ppc64 boot hang when KCOV and KASAN are enabled.
+kasan_early_init() gets called before a PACA is initialised, but the
+KCOV hook expects a valid PACA.
+
+Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://msgid.link/20230710044143.146840-1-bgray@linux.ibm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/mm/kasan/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/mm/kasan/Makefile b/arch/powerpc/mm/kasan/Makefile
+index bb1a5408b86b2..8636b17c6a20f 100644
+--- a/arch/powerpc/mm/kasan/Makefile
++++ b/arch/powerpc/mm/kasan/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ KASAN_SANITIZE := n
++KCOV_INSTRUMENT := n
+ 
+ obj-$(CONFIG_PPC32)           += kasan_init_32.o
+ obj-$(CONFIG_PPC_8xx)         += 8xx.o
+-- 
+2.40.1
+

diff --git a/queue-5.15/rdma-mlx5-return-the-firmware-result-upon-destroying.patch b/queue-5.15/rdma-mlx5-return-the-firmware-result-upon-destroying.patch
new file mode 100644 (file)
index 0000000..1f79685
--- /dev/null
+++ b/queue-5.15/rdma-mlx5-return-the-firmware-result-upon-destroying.patch
@@ -0,0 +1,112 @@
+From 85e6112a8cffa01e6e55d89a74e8ce3b8c659d43 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Jun 2023 13:14:07 +0300
+Subject: RDMA/mlx5: Return the firmware result upon destroying QP/RQ
+
+From: Patrisious Haddad <phaddad@nvidia.com>
+
+[ Upstream commit 22664c06e997087fe37f9ba208008c948571214a ]
+
+Previously when destroying a QP/RQ, the result of the firmware
+destruction function was ignored and upper layers weren't informed
+about the failure.
+Which in turn could lead to various problems since when upper layer
+isn't aware of the failure it continues its operation thinking that the
+related QP/RQ was successfully destroyed while it actually wasn't,
+which could lead to the below kernel WARN.
+
+Currently, we return the correct firmware destruction status to upper
+layers which in case of the RQ would be mlx5_ib_destroy_wq() which
+was already capable of handling RQ destruction failure or in case of
+a QP to destroy_qp_common(), which now would actually warn upon qp
+destruction failure.
+
+WARNING: CPU: 3 PID: 995 at drivers/infiniband/core/rdma_core.c:940 uverbs_destroy_ufile_hw+0xcb/0xe0 [ib_uverbs]
+Modules linked in: xt_conntrack xt_MASQUERADE nf_conntrack_netlink nfnetlink xt_addrtype iptable_nat nf_nat br_netfilter rpcrdma rdma_ucm ib_iser libiscsi scsi_transport_iscsi rdma_cm ib_umad ib_ipoib iw_cm ib_cm mlx5_ib ib_uverbs ib_core overlay mlx5_core fuse
+CPU: 3 PID: 995 Comm: python3 Not tainted 5.16.0-rc5+ #1
+Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014
+RIP: 0010:uverbs_destroy_ufile_hw+0xcb/0xe0 [ib_uverbs]
+Code: 41 5c 41 5d 41 5e e9 44 34 f0 e0 48 89 df e8 4c 77 ff ff 49 8b 86 10 01 00 00 48 85 c0 74 a1 4c 89 e7 ff d0 eb 9a 0f 0b eb c1 <0f> 0b be 04 00 00 00 48 89 df e8 b6 f6 ff ff e9 75 ff ff ff 90 0f
+RSP: 0018:ffff8881533e3e78 EFLAGS: 00010287
+RAX: ffff88811b2cf3e0 RBX: ffff888106209700 RCX: 0000000000000000
+RDX: ffff888106209780 RSI: ffff8881533e3d30 RDI: ffff888109b101a0
+RBP: 0000000000000001 R08: ffff888127cb381c R09: 0de9890000000009
+R10: ffff888127cb3800 R11: 0000000000000000 R12: ffff888106209780
+R13: ffff888106209750 R14: ffff888100f20660 R15: 0000000000000000
+FS:  00007f8be353b740(0000) GS:ffff88852c980000(0000) knlGS:0000000000000000
+CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+CR2: 00007f8bd5b117c0 CR3: 000000012cd8a004 CR4: 0000000000370ea0
+DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+Call Trace:
+ <TASK>
+ ib_uverbs_close+0x1a/0x90 [ib_uverbs]
+ __fput+0x82/0x230
+ task_work_run+0x59/0x90
+ exit_to_user_mode_prepare+0x138/0x140
+ syscall_exit_to_user_mode+0x1d/0x50
+ ? __x64_sys_close+0xe/0x40
+ do_syscall_64+0x4a/0x90
+ entry_SYSCALL_64_after_hwframe+0x44/0xae
+RIP: 0033:0x7f8be3ae0abb
+Code: 03 00 00 00 0f 05 48 3d 00 f0 ff ff 77 41 c3 48 83 ec 18 89 7c 24 0c e8 83 43 f9 ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 c1 43 f9 ff 8b 44
+RSP: 002b:00007ffdb51909c0 EFLAGS: 00000293 ORIG_RAX: 0000000000000003
+RAX: 0000000000000000 RBX: 0000557bb7f7c020 RCX: 00007f8be3ae0abb
+RDX: 0000557bb7c74010 RSI: 0000557bb7f14ca0 RDI: 0000000000000005
+RBP: 0000557bb7fbd598 R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000293 R12: 0000557bb7fbd5b8
+R13: 0000557bb7fbd5a8 R14: 0000000000001000 R15: 0000557bb7f7c020
+ </TASK>
+
+Signed-off-by: Patrisious Haddad <phaddad@nvidia.com>
+Link: https://lore.kernel.org/r/c6df677f931d18090bafbe7f7dbb9524047b7d9b.1685953497.git.leon@kernel.org
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/mlx5/qpc.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/infiniband/hw/mlx5/qpc.c b/drivers/infiniband/hw/mlx5/qpc.c
+index 8844eacf2380e..e508c0753dd37 100644
+--- a/drivers/infiniband/hw/mlx5/qpc.c
++++ b/drivers/infiniband/hw/mlx5/qpc.c
+@@ -297,8 +297,7 @@ int mlx5_core_destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp)
+       MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
+       MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
+       MLX5_SET(destroy_qp_in, in, uid, qp->uid);
+-      mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
+-      return 0;
++      return mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
+ }
+ 
+ int mlx5_core_set_delay_drop(struct mlx5_ib_dev *dev,
+@@ -548,14 +547,14 @@ int mlx5_core_xrcd_dealloc(struct mlx5_ib_dev *dev, u32 xrcdn)
+       return mlx5_cmd_exec_in(dev->mdev, dealloc_xrcd, in);
+ }
+ 
+-static void destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
++static int destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
+ {
+       u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
+ 
+       MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
+       MLX5_SET(destroy_rq_in, in, rqn, rqn);
+       MLX5_SET(destroy_rq_in, in, uid, uid);
+-      mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
++      return mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
+ }
+ 
+ int mlx5_core_create_rq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
+@@ -586,8 +585,7 @@ int mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev *dev,
+                                struct mlx5_core_qp *rq)
+ {
+       destroy_resource_common(dev, rq);
+-      destroy_rq_tracked(dev, rq->qpn, rq->uid);
+-      return 0;
++      return destroy_rq_tracked(dev, rq->qpn, rq->uid);
+ }
+ 
+ static void destroy_sq_tracked(struct mlx5_ib_dev *dev, u32 sqn, u16 uid)
+-- 
+2.40.1
+

diff --git a/queue-5.15/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch b/queue-5.15/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
new file mode 100644 (file)
index 0000000..ab6c17d
--- /dev/null
+++ b/queue-5.15/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
@@ -0,0 +1,243 @@
+From 5dd6d987949cf4c7b045403879cb5bbef31206db Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Jul 2023 15:58:47 +0800
+Subject: ring-buffer: Do not swap cpu_buffer during resize process
+
+From: Chen Lin <chen.lin5@zte.com.cn>
+
+[ Upstream commit 8a96c0288d0737ad77882024974c075345c72011 ]
+
+When ring_buffer_swap_cpu was called during resize process,
+the cpu buffer was swapped in the middle, resulting in incorrect state.
+Continuing to run in the wrong state will result in oops.
+
+This issue can be easily reproduced using the following two scripts:
+/tmp # cat test1.sh
+//#! /bin/sh
+for i in `seq 0 100000`
+do
+         echo 2000 > /sys/kernel/debug/tracing/buffer_size_kb
+         sleep 0.5
+         echo 5000 > /sys/kernel/debug/tracing/buffer_size_kb
+         sleep 0.5
+done
+/tmp # cat test2.sh
+//#! /bin/sh
+for i in `seq 0 100000`
+do
+        echo irqsoff > /sys/kernel/debug/tracing/current_tracer
+        sleep 1
+        echo nop > /sys/kernel/debug/tracing/current_tracer
+        sleep 1
+done
+/tmp # ./test1.sh &
+/tmp # ./test2.sh &
+
+A typical oops log is as follows, sometimes with other different oops logs.
+
+[  231.711293] WARNING: CPU: 0 PID: 9 at kernel/trace/ring_buffer.c:2026 rb_update_pages+0x378/0x3f8
+[  231.713375] Modules linked in:
+[  231.714735] CPU: 0 PID: 9 Comm: kworker/0:1 Tainted: G        W          6.5.0-rc1-00276-g20edcec23f92 #15
+[  231.716750] Hardware name: linux,dummy-virt (DT)
+[  231.718152] Workqueue: events update_pages_handler
+[  231.719714] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[  231.721171] pc : rb_update_pages+0x378/0x3f8
+[  231.722212] lr : rb_update_pages+0x25c/0x3f8
+[  231.723248] sp : ffff800082b9bd50
+[  231.724169] x29: ffff800082b9bd50 x28: ffff8000825f7000 x27: 0000000000000000
+[  231.726102] x26: 0000000000000001 x25: fffffffffffff010 x24: 0000000000000ff0
+[  231.728122] x23: ffff0000c3a0b600 x22: ffff0000c3a0b5c0 x21: fffffffffffffe0a
+[  231.730203] x20: ffff0000c3a0b600 x19: ffff0000c0102400 x18: 0000000000000000
+[  231.732329] x17: 0000000000000000 x16: 0000000000000000 x15: 0000ffffe7aa8510
+[  231.734212] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000002
+[  231.736291] x11: ffff8000826998a8 x10: ffff800082b9baf0 x9 : ffff800081137558
+[  231.738195] x8 : fffffc00030e82c8 x7 : 0000000000000000 x6 : 0000000000000001
+[  231.740192] x5 : ffff0000ffbafe00 x4 : 0000000000000000 x3 : 0000000000000000
+[  231.742118] x2 : 00000000000006aa x1 : 0000000000000001 x0 : ffff0000c0007208
+[  231.744196] Call trace:
+[  231.744892]  rb_update_pages+0x378/0x3f8
+[  231.745893]  update_pages_handler+0x1c/0x38
+[  231.746893]  process_one_work+0x1f0/0x468
+[  231.747852]  worker_thread+0x54/0x410
+[  231.748737]  kthread+0x124/0x138
+[  231.749549]  ret_from_fork+0x10/0x20
+[  231.750434] ---[ end trace 0000000000000000 ]---
+[  233.720486] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
+[  233.721696] Mem abort info:
+[  233.721935]   ESR = 0x0000000096000004
+[  233.722283]   EC = 0x25: DABT (current EL), IL = 32 bits
+[  233.722596]   SET = 0, FnV = 0
+[  233.722805]   EA = 0, S1PTW = 0
+[  233.723026]   FSC = 0x04: level 0 translation fault
+[  233.723458] Data abort info:
+[  233.723734]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
+[  233.724176]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
+[  233.724589]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
+[  233.725075] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000104943000
+[  233.725592] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000
+[  233.726231] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
+[  233.726720] Modules linked in:
+[  233.727007] CPU: 0 PID: 9 Comm: kworker/0:1 Tainted: G        W          6.5.0-rc1-00276-g20edcec23f92 #15
+[  233.727777] Hardware name: linux,dummy-virt (DT)
+[  233.728225] Workqueue: events update_pages_handler
+[  233.728655] pstate: 200000c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[  233.729054] pc : rb_update_pages+0x1a8/0x3f8
+[  233.729334] lr : rb_update_pages+0x154/0x3f8
+[  233.729592] sp : ffff800082b9bd50
+[  233.729792] x29: ffff800082b9bd50 x28: ffff8000825f7000 x27: 0000000000000000
+[  233.730220] x26: 0000000000000000 x25: ffff800082a8b840 x24: ffff0000c0102418
+[  233.730653] x23: 0000000000000000 x22: fffffc000304c880 x21: 0000000000000003
+[  233.731105] x20: 00000000000001f4 x19: ffff0000c0102400 x18: ffff800082fcbc58
+[  233.731727] x17: 0000000000000000 x16: 0000000000000001 x15: 0000000000000001
+[  233.732282] x14: ffff8000825fe0c8 x13: 0000000000000001 x12: 0000000000000000
+[  233.732709] x11: ffff8000826998a8 x10: 0000000000000ae0 x9 : ffff8000801b760c
+[  233.733148] x8 : fefefefefefefeff x7 : 0000000000000018 x6 : ffff0000c03298c0
+[  233.733553] x5 : 0000000000000002 x4 : 0000000000000000 x3 : 0000000000000000
+[  233.733972] x2 : ffff0000c3a0b600 x1 : 0000000000000000 x0 : 0000000000000000
+[  233.734418] Call trace:
+[  233.734593]  rb_update_pages+0x1a8/0x3f8
+[  233.734853]  update_pages_handler+0x1c/0x38
+[  233.735148]  process_one_work+0x1f0/0x468
+[  233.735525]  worker_thread+0x54/0x410
+[  233.735852]  kthread+0x124/0x138
+[  233.736064]  ret_from_fork+0x10/0x20
+[  233.736387] Code: 92400000 910006b5 aa000021 aa0303f7 (f9400060)
+[  233.736959] ---[ end trace 0000000000000000 ]---
+
+After analysis, the seq of the error is as follows [1-5]:
+
+int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+                       int cpu_id)
+{
+       for_each_buffer_cpu(buffer, cpu) {
+               cpu_buffer = buffer->buffers[cpu];
+               //1. get cpu_buffer, aka cpu_buffer(A)
+               ...
+               ...
+               schedule_work_on(cpu,
+                &cpu_buffer->update_pages_work);
+               //2. 'update_pages_work' is queue on 'cpu', cpu_buffer(A) is passed to
+               // update_pages_handler, do the update process, set 'update_done' in
+               // complete(&cpu_buffer->update_done) and to wakeup resize process.
+       //---->
+               //3. Just at this moment, ring_buffer_swap_cpu is triggered,
+               //cpu_buffer(A) be swaped to cpu_buffer(B), the max_buffer.
+               //ring_buffer_swap_cpu is called as the 'Call trace' below.
+
+               Call trace:
+                dump_backtrace+0x0/0x2f8
+                show_stack+0x18/0x28
+                dump_stack+0x12c/0x188
+                ring_buffer_swap_cpu+0x2f8/0x328
+                update_max_tr_single+0x180/0x210
+                check_critical_timing+0x2b4/0x2c8
+                tracer_hardirqs_on+0x1c0/0x200
+                trace_hardirqs_on+0xec/0x378
+                el0_svc_common+0x64/0x260
+                do_el0_svc+0x90/0xf8
+                el0_svc+0x20/0x30
+                el0_sync_handler+0xb0/0xb8
+                el0_sync+0x180/0x1c0
+       //<----
+
+       /* wait for all the updates to complete */
+       for_each_buffer_cpu(buffer, cpu) {
+               cpu_buffer = buffer->buffers[cpu];
+               //4. get cpu_buffer, cpu_buffer(B) is used in the following process,
+               //the state of cpu_buffer(A) and cpu_buffer(B) is totally wrong.
+               //for example, cpu_buffer(A)->update_done will leave be set 1, and will
+               //not 'wait_for_completion' at the next resize round.
+                 if (!cpu_buffer->nr_pages_to_update)
+                       continue;
+
+               if (cpu_online(cpu))
+                       wait_for_completion(&cpu_buffer->update_done);
+               cpu_buffer->nr_pages_to_update = 0;
+       }
+       ...
+}
+       //5. the state of cpu_buffer(A) and cpu_buffer(B) is totally wrong,
+       //Continuing to run in the wrong state, then oops occurs.
+
+Link: https://lore.kernel.org/linux-trace-kernel/202307191558478409990@zte.com.cn
+
+Signed-off-by: Chen Lin <chen.lin5@zte.com.cn>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/ring_buffer.c | 14 +++++++++++++-
+ kernel/trace/trace.c       |  3 ++-
+ 2 files changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index e1cef097b0df5..db7cefd196cec 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -535,6 +535,7 @@ struct trace_buffer {
+       unsigned                        flags;
+       int                             cpus;
+       atomic_t                        record_disabled;
++      atomic_t                        resizing;
+       cpumask_var_t                   cpumask;
+ 
+       struct lock_class_key           *reader_lock_key;
+@@ -2137,7 +2138,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+ 
+       /* prevent another thread from changing buffer sizes */
+       mutex_lock(&buffer->mutex);
+-
++      atomic_inc(&buffer->resizing);
+ 
+       if (cpu_id == RING_BUFFER_ALL_CPUS) {
+               /*
+@@ -2276,6 +2277,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+               atomic_dec(&buffer->record_disabled);
+       }
+ 
++      atomic_dec(&buffer->resizing);
+       mutex_unlock(&buffer->mutex);
+       return 0;
+ 
+@@ -2296,6 +2298,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+               }
+       }
+  out_err_unlock:
++      atomic_dec(&buffer->resizing);
+       mutex_unlock(&buffer->mutex);
+       return err;
+ }
+@@ -5497,6 +5500,15 @@ int ring_buffer_swap_cpu(struct trace_buffer *buffer_a,
+       if (local_read(&cpu_buffer_b->committing))
+               goto out_dec;
+ 
++      /*
++       * When resize is in progress, we cannot swap it because
++       * it will mess the state of the cpu buffer.
++       */
++      if (atomic_read(&buffer_a->resizing))
++              goto out_dec;
++      if (atomic_read(&buffer_b->resizing))
++              goto out_dec;
++
+       buffer_a->buffers[cpu] = cpu_buffer_b;
+       buffer_b->buffers[cpu] = cpu_buffer_a;
+ 
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index ae7005af78c34..d4c381f06b7b2 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -1872,9 +1872,10 @@ update_max_tr_single(struct trace_array *tr, struct task_struct *tsk, int cpu)
+                * place on this CPU. We fail to record, but we reset
+                * the max trace buffer (no one writes directly to it)
+                * and flag that it failed.
++               * Another reason is resize is in progress.
+                */
+               trace_array_printk_buf(tr->max_buffer.buffer, _THIS_IP_,
+-                      "Failed to swap buffers due to commit in progress\n");
++                      "Failed to swap buffers due to commit or resize in progress\n");
+       }
+ 
+       WARN_ON_ONCE(ret && ret != -EAGAIN && ret != -EBUSY);
+-- 
+2.40.1
+

diff --git a/queue-5.15/selftests-forwarding-tc_actions-cleanup-temporary-fi.patch b/queue-5.15/selftests-forwarding-tc_actions-cleanup-temporary-fi.patch
new file mode 100644 (file)
index 0000000..261d77b
--- /dev/null
+++ b/queue-5.15/selftests-forwarding-tc_actions-cleanup-temporary-fi.patch
@@ -0,0 +1,86 @@
+From e220e048c361cfb6fb2ce347835e5e9fc5793505 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 14 Feb 2023 10:52:37 +0100
+Subject: selftests: forwarding: tc_actions: cleanup temporary files when test
+ is aborted
+
+From: Davide Caratti <dcaratti@redhat.com>
+
+[ Upstream commit f58531716ced8975a4ade108ef4af35f98722af7 ]
+
+remove temporary files created by 'mirred_egress_to_ingress_tcp' test
+in the cleanup() handler. Also, change variable names to avoid clashing
+with globals from lib.sh.
+
+Suggested-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Davide Caratti <dcaratti@redhat.com>
+Link: https://lore.kernel.org/r/091649045a017fc00095ecbb75884e5681f7025f.1676368027.git.dcaratti@redhat.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: 5e8670610b93 ("selftests: forwarding: tc_actions: Use ncat instead of nc")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../selftests/net/forwarding/tc_actions.sh       | 16 ++++++++++------
+ 1 file changed, 10 insertions(+), 6 deletions(-)
+
+diff --git a/tools/testing/selftests/net/forwarding/tc_actions.sh b/tools/testing/selftests/net/forwarding/tc_actions.sh
+index 1e27031288c81..9c2aca8a4b8de 100755
+--- a/tools/testing/selftests/net/forwarding/tc_actions.sh
++++ b/tools/testing/selftests/net/forwarding/tc_actions.sh
+@@ -155,10 +155,10 @@ gact_trap_test()
+ 
+ mirred_egress_to_ingress_tcp_test()
+ {
+-      local tmpfile=$(mktemp) tmpfile1=$(mktemp)
++      mirred_e2i_tf1=$(mktemp) mirred_e2i_tf2=$(mktemp)
+ 
+       RET=0
+-      dd conv=sparse status=none if=/dev/zero bs=1M count=2 of=$tmpfile
++      dd conv=sparse status=none if=/dev/zero bs=1M count=2 of=$mirred_e2i_tf1
+       tc filter add dev $h1 protocol ip pref 100 handle 100 egress flower \
+               $tcflags ip_proto tcp src_ip 192.0.2.1 dst_ip 192.0.2.2 \
+                       action ct commit nat src addr 192.0.2.2 pipe \
+@@ -174,11 +174,11 @@ mirred_egress_to_ingress_tcp_test()
+               ip_proto icmp \
+                       action drop
+ 
+-      ip vrf exec v$h1 nc --recv-only -w10 -l -p 12345 -o $tmpfile1  &
++      ip vrf exec v$h1 nc --recv-only -w10 -l -p 12345 -o $mirred_e2i_tf2  &
+       local rpid=$!
+-      ip vrf exec v$h1 nc -w1 --send-only 192.0.2.2 12345 <$tmpfile
++      ip vrf exec v$h1 nc -w1 --send-only 192.0.2.2 12345 <$mirred_e2i_tf1
+       wait -n $rpid
+-      cmp -s $tmpfile $tmpfile1
++      cmp -s $mirred_e2i_tf1 $mirred_e2i_tf2
+       check_err $? "server output check failed"
+ 
+       $MZ $h1 -c 10 -p 64 -a $h1mac -b $h1mac -A 192.0.2.1 -B 192.0.2.1 \
+@@ -195,7 +195,7 @@ mirred_egress_to_ingress_tcp_test()
+       tc filter del dev $h1 egress protocol ip pref 101 handle 101 flower
+       tc filter del dev $h1 ingress protocol ip pref 102 handle 102 flower
+ 
+-      rm -f $tmpfile $tmpfile1
++      rm -f $mirred_e2i_tf1 $mirred_e2i_tf2
+       log_test "mirred_egress_to_ingress_tcp ($tcflags)"
+ }
+ 
+@@ -224,6 +224,8 @@ setup_prepare()
+ 
+ cleanup()
+ {
++      local tf
++
+       pre_cleanup
+ 
+       switch_destroy
+@@ -234,6 +236,8 @@ cleanup()
+ 
+       ip link set $swp2 address $swp2origmac
+       ip link set $swp1 address $swp1origmac
++
++      for tf in $mirred_e2i_tf1 $mirred_e2i_tf2; do rm -f $tf; done
+ }
+ 
+ mirred_egress_redirect_test()
+-- 
+2.40.1
+

diff --git a/queue-5.15/selftests-forwarding-tc_actions-use-ncat-instead-of-.patch b/queue-5.15/selftests-forwarding-tc_actions-use-ncat-instead-of-.patch
new file mode 100644 (file)
index 0000000..7a1747c
--- /dev/null
+++ b/queue-5.15/selftests-forwarding-tc_actions-use-ncat-instead-of-.patch
@@ -0,0 +1,84 @@
+From 72755740c40a934d03c80da2fbc1573751799cf8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 8 Aug 2023 17:14:57 +0300
+Subject: selftests: forwarding: tc_actions: Use ncat instead of nc
+
+From: Ido Schimmel <idosch@nvidia.com>
+
+[ Upstream commit 5e8670610b93158ffacc3241f835454ff26a3469 ]
+
+The test relies on 'nc' being the netcat version from the nmap project.
+While this seems to be the case on Fedora, it is not the case on Ubuntu,
+resulting in failures such as [1].
+
+Fix by explicitly using the 'ncat' utility from the nmap project and the
+skip the test in case it is not installed.
+
+[1]
+ # timeout set to 0
+ # selftests: net/forwarding: tc_actions.sh
+ # TEST: gact drop and ok (skip_hw)                                    [ OK ]
+ # TEST: mirred egress flower redirect (skip_hw)                       [ OK ]
+ # TEST: mirred egress flower mirror (skip_hw)                         [ OK ]
+ # TEST: mirred egress matchall mirror (skip_hw)                       [ OK ]
+ # TEST: mirred_egress_to_ingress (skip_hw)                            [ OK ]
+ # nc: invalid option -- '-'
+ # usage: nc [-46CDdFhklNnrStUuvZz] [-I length] [-i interval] [-M ttl]
+ #         [-m minttl] [-O length] [-P proxy_username] [-p source_port]
+ #         [-q seconds] [-s sourceaddr] [-T keyword] [-V rtable] [-W recvlimit]
+ #         [-w timeout] [-X proxy_protocol] [-x proxy_address[:port]]
+ #         [destination] [port]
+ # nc: invalid option -- '-'
+ # usage: nc [-46CDdFhklNnrStUuvZz] [-I length] [-i interval] [-M ttl]
+ #         [-m minttl] [-O length] [-P proxy_username] [-p source_port]
+ #         [-q seconds] [-s sourceaddr] [-T keyword] [-V rtable] [-W recvlimit]
+ #         [-w timeout] [-X proxy_protocol] [-x proxy_address[:port]]
+ #         [destination] [port]
+ # TEST: mirred_egress_to_ingress_tcp (skip_hw)                        [FAIL]
+ #       server output check failed
+ # INFO: Could not test offloaded functionality
+ not ok 80 selftests: net/forwarding: tc_actions.sh # exit=1
+
+Fixes: ca22da2fbd69 ("act_mirred: use the backlog for nested calls to mirred ingress")
+Reported-by: Mirsad Todorovac <mirsad.todorovac@alu.unizg.hr>
+Closes: https://lore.kernel.org/netdev/adc5e40d-d040-a65e-eb26-edf47dac5b02@alu.unizg.hr/
+Signed-off-by: Ido Schimmel <idosch@nvidia.com>
+Reviewed-by: Petr Machata <petrm@nvidia.com>
+Tested-by: Mirsad Todorovac <mirsad.todorovac@alu.unizg.hr>
+Reviewed-by: Hangbin Liu <liuhangbin@gmail.com>
+Acked-by: Nikolay Aleksandrov <razor@blackwall.org>
+Link: https://lore.kernel.org/r/20230808141503.4060661-12-idosch@nvidia.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/net/forwarding/tc_actions.sh | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/tools/testing/selftests/net/forwarding/tc_actions.sh b/tools/testing/selftests/net/forwarding/tc_actions.sh
+index 9c2aca8a4b8de..dd02ed4cacacb 100755
+--- a/tools/testing/selftests/net/forwarding/tc_actions.sh
++++ b/tools/testing/selftests/net/forwarding/tc_actions.sh
+@@ -8,6 +8,8 @@ NUM_NETIFS=4
+ source tc_common.sh
+ source lib.sh
+ 
++require_command ncat
++
+ tcflags="skip_hw"
+ 
+ h1_create()
+@@ -174,9 +176,9 @@ mirred_egress_to_ingress_tcp_test()
+               ip_proto icmp \
+                       action drop
+ 
+-      ip vrf exec v$h1 nc --recv-only -w10 -l -p 12345 -o $mirred_e2i_tf2  &
++      ip vrf exec v$h1 ncat --recv-only -w10 -l -p 12345 -o $mirred_e2i_tf2 &
+       local rpid=$!
+-      ip vrf exec v$h1 nc -w1 --send-only 192.0.2.2 12345 <$mirred_e2i_tf1
++      ip vrf exec v$h1 ncat -w1 --send-only 192.0.2.2 12345 <$mirred_e2i_tf1
+       wait -n $rpid
+       cmp -s $mirred_e2i_tf1 $mirred_e2i_tf2
+       check_err $? "server output check failed"
+-- 
+2.40.1
+

diff --git a/queue-5.15/series b/queue-5.15/series
new file mode 100644 (file)
index 0000000..dbeff82
--- /dev/null
+++ b/queue-5.15/series
@@ -0,0 +1,74 @@
+mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
+selftests-forwarding-tc_actions-cleanup-temporary-fi.patch
+selftests-forwarding-tc_actions-use-ncat-instead-of-.patch
+macsec-fix-traffic-counters-statistics.patch
+macsec-use-dev_stats_inc.patch
+net-tls-perform-immediate-device-ctx-cleanup-when-po.patch
+net-tls-multi-threaded-calls-to-tx-tls_dev_del.patch
+net-tls-avoid-discarding-data-on-record-close.patch
+pci-tegra194-fix-possible-array-out-of-bounds-access.patch
+arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
+iopoll-call-cpu_relax-in-busy-loops.patch
+asoc-sof-intel-fix-soundwire-hdaudio-mutual-exclusio.patch
+dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
+hid-logitech-hidpp-add-usb-and-bluetooth-ids-for-the.patch
+drm-amdgpu-install-stub-fence-into-potential-unused-.patch
+hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
+rdma-mlx5-return-the-firmware-result-upon-destroying.patch
+ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
+smb-client-fix-warning-in-cifs_smb3_do_mount.patch
+media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
+usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
+media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
+thunderbolt-read-retimer-nvm-authentication-status-p.patch
+usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
+usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
+gfs2-fix-possible-data-races-in-gfs2_show_options.patch
+pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
+firewire-net-fix-use-after-free-in-fwnet_finish_inco.patch
+watchdog-sp5100_tco-support-hygon-fch-sch-server-con.patch
+bluetooth-l2cap-fix-use-after-free.patch
+bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
+drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
+fs-ntfs3-enhance-sanity-check-while-generating-attr_.patch
+fs-ntfs3-fix-possible-null-pointer-dereferences-in-m.patch
+fs-ntfs3-mark-ntfs-dirty-when-on-disk-struct-is-corr.patch
+alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
+alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
+apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
+powerpc-kasan-disable-kcov-in-kasan-code.patch
+ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
+iio-add-addac-subdirectory.patch
+iio-adc-stx104-utilize-iomap-interface.patch
+iio-adc-stx104-implement-and-utilize-register-struct.patch
+iio-stx104-move-to-addac-subdirectory.patch
+iio-addac-stx104-fix-race-condition-for-stx104_write.patch
+iio-addac-stx104-fix-race-condition-when-converting-.patch
+xsk-add-cb-area-to-struct-xdp_buff_xsk.patch
+igc-read-before-write-to-srrctl-register.patch
+arm-dts-aspeed-asrock-correct-firmware-flash-spi-clo.patch
+drm-amd-display-save-restore-hdcp-state-when-display.patch
+drm-amd-display-phase3-mst-hdcp-for-multiple-display.patch
+drm-amd-display-fix-access-hdcp_workqueue-assert.patch
+usb-dwc3-gadget-synchronize-irq-between-soft-connect.patch
+usb-dwc3-remove-dwc3-locking-during-gadget-suspend-r.patch
+usb-dwc3-fix-typos-in-gadget.c.patch
+usb-dwc3-gadget-drop-dead-hibernation-code.patch
+usb-dwc3-gadget-improve-dwc3_gadget_suspend-and-dwc3.patch
+phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
+phy-qcom-qmp-combo-fix-init-count-imbalance.patch
+phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
+tty-serial-fsl_lpuart-add-i.mxrt1050-support.patch
+tty-serial-fsl_lpuart-make-rx_watermark-configurable.patch
+tty-serial-fsl_lpuart-reduce-rx-watermark-to-0-on-ls.patch
+usb-dwc3-qcom-fix-null-deref-on-suspend.patch
+usb-dwc3-fix-use-after-free-on-core-driver-unbind.patch
+mmc-sdhci-spear-fix-deferred-probing.patch
+mmc-bcm2835-fix-deferred-probing.patch
+mmc-sunxi-fix-deferred-probing.patch
+net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch
+arm-dts-imx6sll-fixup-of-operating-points.patch
+arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch
+btrfs-move-out-now-unused-bg-from-the-reclaim-list.patch
+can-raw-fix-receiver-memory-leak.patch
+can-raw-fix-lockdep-issue-in-raw_release.patch

diff --git a/queue-5.15/smb-client-fix-warning-in-cifs_smb3_do_mount.patch b/queue-5.15/smb-client-fix-warning-in-cifs_smb3_do_mount.patch
new file mode 100644 (file)
index 0000000..02afda7
--- /dev/null
+++ b/queue-5.15/smb-client-fix-warning-in-cifs_smb3_do_mount.patch
@@ -0,0 +1,88 @@
+From dd3ab8d76380fb292235dff0b69ad1bfbb32e8b5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Jun 2023 16:24:37 -0300
+Subject: smb: client: fix warning in cifs_smb3_do_mount()
+
+From: Paulo Alcantara <pc@manguebit.com>
+
+[ Upstream commit 12c30f33cc6769bf411088a2872843c4f9ea32f9 ]
+
+This fixes the following warning reported by kernel test robot
+
+  fs/smb/client/cifsfs.c:982 cifs_smb3_do_mount() warn: possible
+  memory leak of 'cifs_sb'
+
+Link: https://lore.kernel.org/all/202306170124.CtQqzf0I-lkp@intel.com/
+Signed-off-by: Paulo Alcantara (SUSE) <pc@manguebit.com>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/cifs/cifsfs.c | 28 ++++++++++------------------
+ 1 file changed, 10 insertions(+), 18 deletions(-)
+
+diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c
+index c9481289266ca..b5ae209539ff1 100644
+--- a/fs/cifs/cifsfs.c
++++ b/fs/cifs/cifsfs.c
+@@ -848,11 +848,11 @@ struct dentry *
+ cifs_smb3_do_mount(struct file_system_type *fs_type,
+             int flags, struct smb3_fs_context *old_ctx)
+ {
+-      int rc;
+-      struct super_block *sb = NULL;
+-      struct cifs_sb_info *cifs_sb = NULL;
+       struct cifs_mnt_data mnt_data;
++      struct cifs_sb_info *cifs_sb;
++      struct super_block *sb;
+       struct dentry *root;
++      int rc;
+ 
+       /*
+        * Prints in Kernel / CIFS log the attempted mount operation
+@@ -863,11 +863,9 @@ cifs_smb3_do_mount(struct file_system_type *fs_type,
+       else
+               cifs_info("Attempting to mount %s\n", old_ctx->UNC);
+ 
+-      cifs_sb = kzalloc(sizeof(struct cifs_sb_info), GFP_KERNEL);
+-      if (cifs_sb == NULL) {
+-              root = ERR_PTR(-ENOMEM);
+-              goto out;
+-      }
++      cifs_sb = kzalloc(sizeof(*cifs_sb), GFP_KERNEL);
++      if (!cifs_sb)
++              return ERR_PTR(-ENOMEM);
+ 
+       cifs_sb->ctx = kzalloc(sizeof(struct smb3_fs_context), GFP_KERNEL);
+       if (!cifs_sb->ctx) {
+@@ -910,10 +908,8 @@ cifs_smb3_do_mount(struct file_system_type *fs_type,
+ 
+       sb = sget(fs_type, cifs_match_super, cifs_set_super, flags, &mnt_data);
+       if (IS_ERR(sb)) {
+-              root = ERR_CAST(sb);
+               cifs_umount(cifs_sb);
+-              cifs_sb = NULL;
+-              goto out;
++              return ERR_CAST(sb);
+       }
+ 
+       if (sb->s_root) {
+@@ -944,13 +940,9 @@ cifs_smb3_do_mount(struct file_system_type *fs_type,
+       deactivate_locked_super(sb);
+       return root;
+ out:
+-      if (cifs_sb) {
+-              if (!sb || IS_ERR(sb)) {  /* otherwise kill_sb will handle */
+-                      kfree(cifs_sb->prepath);
+-                      smb3_cleanup_fs_context(cifs_sb->ctx);
+-                      kfree(cifs_sb);
+-              }
+-      }
++      kfree(cifs_sb->prepath);
++      smb3_cleanup_fs_context(cifs_sb->ctx);
++      kfree(cifs_sb);
+       return root;
+ }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/thunderbolt-read-retimer-nvm-authentication-status-p.patch b/queue-5.15/thunderbolt-read-retimer-nvm-authentication-status-p.patch
new file mode 100644 (file)
index 0000000..b145d78
--- /dev/null
+++ b/queue-5.15/thunderbolt-read-retimer-nvm-authentication-status-p.patch
@@ -0,0 +1,73 @@
+From 031562d24cfb06543ea4405520b5c2b6b47b1926 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 May 2023 14:46:44 +0300
+Subject: thunderbolt: Read retimer NVM authentication status prior
+ tb_retimer_set_inbound_sbtx()
+
+From: Mika Westerberg <mika.westerberg@linux.intel.com>
+
+[ Upstream commit 1402ba08abae5cfa583ff1a40b99c098a0532d41 ]
+
+According to the USB4 retimer guide the correct order is immediately
+after sending ENUMERATE_RETIMERS so update the code to follow this.
+
+Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/thunderbolt/retimer.c | 29 +++++++++++++++++++++--------
+ 1 file changed, 21 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/thunderbolt/retimer.c b/drivers/thunderbolt/retimer.c
+index 566c03105fb8d..1b7ab0bbd1328 100644
+--- a/drivers/thunderbolt/retimer.c
++++ b/drivers/thunderbolt/retimer.c
+@@ -208,6 +208,21 @@ static ssize_t nvm_authenticate_show(struct device *dev,
+       return ret;
+ }
+ 
++static void tb_retimer_nvm_authenticate_status(struct tb_port *port, u32 *status)
++{
++      int i;
++
++      tb_port_dbg(port, "reading NVM authentication status of retimers\n");
++
++      /*
++       * Before doing anything else, read the authentication status.
++       * If the retimer has it set, store it for the new retimer
++       * device instance.
++       */
++      for (i = 1; i <= TB_MAX_RETIMER_INDEX; i++)
++              usb4_port_retimer_nvm_authenticate_status(port, i, &status[i]);
++}
++
+ static void tb_retimer_set_inbound_sbtx(struct tb_port *port)
+ {
+       int i;
+@@ -481,18 +496,16 @@ int tb_retimer_scan(struct tb_port *port, bool add)
+               return ret;
+ 
+       /*
+-       * Enable sideband channel for each retimer. We can do this
+-       * regardless whether there is device connected or not.
++       * Immediately after sending enumerate retimers read the
++       * authentication status of each retimer.
+        */
+-      tb_retimer_set_inbound_sbtx(port);
++      tb_retimer_nvm_authenticate_status(port, status);
+ 
+       /*
+-       * Before doing anything else, read the authentication status.
+-       * If the retimer has it set, store it for the new retimer
+-       * device instance.
++       * Enable sideband channel for each retimer. We can do this
++       * regardless whether there is device connected or not.
+        */
+-      for (i = 1; i <= TB_MAX_RETIMER_INDEX; i++)
+-              usb4_port_retimer_nvm_authenticate_status(port, i, &status[i]);
++      tb_retimer_set_inbound_sbtx(port);
+ 
+       for (i = 1; i <= TB_MAX_RETIMER_INDEX; i++) {
+               /*
+-- 
+2.40.1
+

diff --git a/queue-5.15/tty-serial-fsl_lpuart-add-i.mxrt1050-support.patch b/queue-5.15/tty-serial-fsl_lpuart-add-i.mxrt1050-support.patch
new file mode 100644 (file)
index 0000000..20adaca
--- /dev/null
+++ b/queue-5.15/tty-serial-fsl_lpuart-add-i.mxrt1050-support.patch
@@ -0,0 +1,64 @@
+From 596ce9c1ee26df00ced54376b4985cef0b968b6d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 15 Dec 2021 17:05:36 -0500
+Subject: tty: serial: fsl_lpuart: Add i.MXRT1050 support
+
+From: Jesse Taube <mr.bossman075@gmail.com>
+
+[ Upstream commit 443df57b31d14a920f23eaa265f4cb0dc3f94823 ]
+
+Add support for i.MXRT1050's uart.
+
+Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
+Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
+Link: https://lore.kernel.org/r/20211215220538.4180616-8-Mr.Bossman075@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: a82c3df955f8 ("tty: serial: fsl_lpuart: reduce RX watermark to 0 on LS1028A")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/fsl_lpuart.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index b0b27808c7c37..bf709ea93ec97 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -246,6 +246,7 @@ enum lpuart_type {
+       LS1028A_LPUART,
+       IMX7ULP_LPUART,
+       IMX8QXP_LPUART,
++      IMXRT1050_LPUART,
+ };
+ 
+ struct lpuart_port {
+@@ -308,6 +309,11 @@ static struct lpuart_soc_data imx8qxp_data = {
+       .iotype = UPIO_MEM32,
+       .reg_off = IMX_REG_OFF,
+ };
++static struct lpuart_soc_data imxrt1050_data = {
++      .devtype = IMXRT1050_LPUART,
++      .iotype = UPIO_MEM32,
++      .reg_off = IMX_REG_OFF,
++};
+ 
+ static const struct of_device_id lpuart_dt_ids[] = {
+       { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
+@@ -315,6 +321,7 @@ static const struct of_device_id lpuart_dt_ids[] = {
+       { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
+       { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
+       { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
++      { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
+@@ -2634,6 +2641,7 @@ OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup)
+ OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
+ OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
+ OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
++OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
+ EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
+ EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/tty-serial-fsl_lpuart-make-rx_watermark-configurable.patch b/queue-5.15/tty-serial-fsl_lpuart-make-rx_watermark-configurable.patch
new file mode 100644 (file)
index 0000000..0ec684f
--- /dev/null
+++ b/queue-5.15/tty-serial-fsl_lpuart-make-rx_watermark-configurable.patch
@@ -0,0 +1,111 @@
+From be1b5fa87112e48ee00e6feae3a7797a789d07f0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 30 Jan 2023 14:44:44 +0800
+Subject: tty: serial: fsl_lpuart: make rx_watermark configurable for different
+ platforms
+
+From: Sherry Sun <sherry.sun@nxp.com>
+
+[ Upstream commit 34ebb26f12a84b744f43c5c4869516f122a2dfaa ]
+
+Add rx_watermark parameter for struct lpuart_port to make the receive
+watermark configurable for different platforms.
+No function changed.
+
+Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
+Link: https://lore.kernel.org/r/20230130064449.9564-2-sherry.sun@nxp.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: a82c3df955f8 ("tty: serial: fsl_lpuart: reduce RX watermark to 0 on LS1028A")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/fsl_lpuart.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index bf709ea93ec97..380d9237989b2 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -257,6 +257,7 @@ struct lpuart_port {
+       unsigned int            txfifo_size;
+       unsigned int            rxfifo_size;
+ 
++      u8                      rx_watermark;
+       bool                    lpuart_dma_tx_use;
+       bool                    lpuart_dma_rx_use;
+       struct dma_chan         *dma_tx_chan;
+@@ -281,38 +282,45 @@ struct lpuart_soc_data {
+       enum lpuart_type devtype;
+       char iotype;
+       u8 reg_off;
++      u8 rx_watermark;
+ };
+ 
+ static const struct lpuart_soc_data vf_data = {
+       .devtype = VF610_LPUART,
+       .iotype = UPIO_MEM,
++      .rx_watermark = 1,
+ };
+ 
+ static const struct lpuart_soc_data ls1021a_data = {
+       .devtype = LS1021A_LPUART,
+       .iotype = UPIO_MEM32BE,
++      .rx_watermark = 1,
+ };
+ 
+ static const struct lpuart_soc_data ls1028a_data = {
+       .devtype = LS1028A_LPUART,
+       .iotype = UPIO_MEM32,
++      .rx_watermark = 1,
+ };
+ 
+ static struct lpuart_soc_data imx7ulp_data = {
+       .devtype = IMX7ULP_LPUART,
+       .iotype = UPIO_MEM32,
+       .reg_off = IMX_REG_OFF,
++      .rx_watermark = 1,
+ };
+ 
+ static struct lpuart_soc_data imx8qxp_data = {
+       .devtype = IMX8QXP_LPUART,
+       .iotype = UPIO_MEM32,
+       .reg_off = IMX_REG_OFF,
++      .rx_watermark = 1,
+ };
+ static struct lpuart_soc_data imxrt1050_data = {
+       .devtype = IMXRT1050_LPUART,
+       .iotype = UPIO_MEM32,
+       .reg_off = IMX_REG_OFF,
++      .rx_watermark = 1,
+ };
+ 
+ static const struct of_device_id lpuart_dt_ids[] = {
+@@ -1556,7 +1564,7 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
+       }
+ 
+       writeb(0, sport->port.membase + UARTTWFIFO);
+-      writeb(1, sport->port.membase + UARTRWFIFO);
++      writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
+ 
+       /* Restore cr2 */
+       writeb(cr2_saved, sport->port.membase + UARTCR2);
+@@ -1591,7 +1599,8 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
+       lpuart32_write(&sport->port, val, UARTFIFO);
+ 
+       /* set the watermark */
+-      val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
++      val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
++            (0x0 << UARTWATER_TXWATER_OFF);
+       lpuart32_write(&sport->port, val, UARTWATER);
+ 
+       /* Restore cr2 */
+@@ -2736,6 +2745,7 @@ static int lpuart_probe(struct platform_device *pdev)
+       sport->port.dev = &pdev->dev;
+       sport->port.type = PORT_LPUART;
+       sport->devtype = sdata->devtype;
++      sport->rx_watermark = sdata->rx_watermark;
+       ret = platform_get_irq(pdev, 0);
+       if (ret < 0)
+               return ret;
+-- 
+2.40.1
+

diff --git a/queue-5.15/tty-serial-fsl_lpuart-reduce-rx-watermark-to-0-on-ls.patch b/queue-5.15/tty-serial-fsl_lpuart-reduce-rx-watermark-to-0-on-ls.patch
new file mode 100644 (file)
index 0000000..e50aa01
--- /dev/null
+++ b/queue-5.15/tty-serial-fsl_lpuart-reduce-rx-watermark-to-0-on-ls.patch
@@ -0,0 +1,46 @@
+From 4a80500d17d4872ca1c96bcfa8f52f3a59f413cf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Jun 2023 14:13:34 +0200
+Subject: tty: serial: fsl_lpuart: reduce RX watermark to 0 on LS1028A
+
+From: Robert Hodaszi <robert.hodaszi@digi.com>
+
+[ Upstream commit a82c3df955f8c1c726e4976527aa6ae924a67dd9 ]
+
+LS1028A is using DMA with LPUART. Having RX watermark set to 1, means
+DMA transactions are started only after receiving the second character.
+
+On other platforms with newer LPUART IP, Receiver Idle Empty function
+initiates the DMA request after the receiver is idling for 4 characters.
+But this feature is missing on LS1028A, which is causing a 1-character
+delay in the RX direction on this platform.
+
+Set RX watermark to 0 to initiate RX DMA after each character.
+
+Link: https://lore.kernel.org/linux-serial/20230607103459.1222426-1-robert.hodaszi@digi.com/
+Fixes: 9ad9df844754 ("tty: serial: fsl_lpuart: Fix the wrong RXWATER setting for rx dma case")
+Cc: stable <stable@kernel.org>
+Signed-off-by: Robert Hodaszi <robert.hodaszi@digi.com>
+Message-ID: <20230609121334.1878626-1-robert.hodaszi@digi.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/fsl_lpuart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index 380d9237989b2..74b445fb065bd 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -300,7 +300,7 @@ static const struct lpuart_soc_data ls1021a_data = {
+ static const struct lpuart_soc_data ls1028a_data = {
+       .devtype = LS1028A_LPUART,
+       .iotype = UPIO_MEM32,
+-      .rx_watermark = 1,
++      .rx_watermark = 0,
+ };
+ 
+ static struct lpuart_soc_data imx7ulp_data = {
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch b/queue-5.15/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
new file mode 100644 (file)
index 0000000..d956d66
--- /dev/null
+++ b/queue-5.15/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
@@ -0,0 +1,41 @@
+From 2d8509860db0448c16d294343559e269e1dee250 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 May 2023 16:19:07 +0800
+Subject: usb: chipidea: imx: add missing USB PHY DPDM wakeup setting
+
+From: Xu Yang <xu.yang_2@nxp.com>
+
+[ Upstream commit 53d061c19dc4cb68409df6dc11c40389c8c42a75 ]
+
+USB PHY DPDM wakeup bit is enabled by default, when USB wakeup
+is not required(/sys/.../wakeup is disabled), this bit should be
+disabled, otherwise we will have unexpected wakeup if do USB device
+connect/disconnect while system sleep.
+This bit can be enabled for both host and device mode.
+
+Signed-off-by: Li Jun <jun.li@nxp.com>
+Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
+Acked-by: Peter Chen <peter.chen@kernel.org>
+Message-ID: <20230517081907.3410465-3-xu.yang_2@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/chipidea/usbmisc_imx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
+index bac0f5458cab9..2318c7906acdb 100644
+--- a/drivers/usb/chipidea/usbmisc_imx.c
++++ b/drivers/usb/chipidea/usbmisc_imx.c
+@@ -135,7 +135,7 @@
+ #define TXVREFTUNE0_MASK              (0xf << 20)
+ 
+ #define MX6_USB_OTG_WAKEUP_BITS (MX6_BM_WAKEUP_ENABLE | MX6_BM_VBUS_WAKEUP | \
+-                               MX6_BM_ID_WAKEUP)
++                               MX6_BM_ID_WAKEUP | MX6SX_BM_DPDM_WAKEUP_EN)
+ 
+ struct usbmisc_ops {
+       /* It's called once when probe a usb device */
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch b/queue-5.15/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
new file mode 100644 (file)
index 0000000..aa1c106
--- /dev/null
+++ b/queue-5.15/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
@@ -0,0 +1,49 @@
+From d1369070df80199453cf0253ce88be2d15eb7074 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 18:40:07 +0800
+Subject: usb: chipidea: imx: don't request QoS for imx8ulp
+
+From: Xu Yang <xu.yang_2@nxp.com>
+
+[ Upstream commit 9a070e8e208995a9d638b538ed7abf28bd6ea6f0 ]
+
+Use dedicated imx8ulp usb compatible to remove QoS request
+since imx8ulp has no such limitation of imx7ulp: DMA will
+not work if system enters idle.
+
+Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
+Signed-off-by: Li Jun <jun.li@nxp.com>
+Acked-by: Peter Chen <peter.chen@kernel.org>
+Message-ID: <20230530104007.1294702-2-xu.yang_2@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/chipidea/ci_hdrc_imx.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
+index 097142ffb1842..669e7606651ab 100644
+--- a/drivers/usb/chipidea/ci_hdrc_imx.c
++++ b/drivers/usb/chipidea/ci_hdrc_imx.c
+@@ -70,6 +70,10 @@ static const struct ci_hdrc_imx_platform_flag imx7ulp_usb_data = {
+               CI_HDRC_PMQOS,
+ };
+ 
++static const struct ci_hdrc_imx_platform_flag imx8ulp_usb_data = {
++      .flags = CI_HDRC_SUPPORTS_RUNTIME_PM,
++};
++
+ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
+       { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
+       { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
+@@ -80,6 +84,7 @@ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
+       { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data},
+       { .compatible = "fsl,imx7d-usb", .data = &imx7d_usb_data},
+       { .compatible = "fsl,imx7ulp-usb", .data = &imx7ulp_usb_data},
++      { .compatible = "fsl,imx8ulp-usb", .data = &imx8ulp_usb_data},
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, ci_hdrc_imx_dt_ids);
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-fix-typos-in-gadget.c.patch b/queue-5.15/usb-dwc3-fix-typos-in-gadget.c.patch
new file mode 100644 (file)
index 0000000..afcd0a1
--- /dev/null
+++ b/queue-5.15/usb-dwc3-fix-typos-in-gadget.c.patch
@@ -0,0 +1,47 @@
+From b28037aede2699c29eda2400cc3a2c8365f46d72 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 19:56:49 +0530
+Subject: usb: dwc3: Fix typos in gadget.c
+
+From: Kushagra Verma <kushagra765@outlook.com>
+
+[ Upstream commit af870d93c706c302a8742d7c751a60a832f7bc64 ]
+
+Fixes the following two typos:
+   1. reinitate -> reinitiate
+   2. revison -> revision
+
+Signed-off-by: Kushagra Verma <kushagra765@outlook.com>
+Link: https://lore.kernel.org/r/HK0PR01MB280110FAB74B4B2ACE32EA5FF8479@HK0PR01MB2801.apcprd01.prod.exchangelabs.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: c8540870af4c ("usb: dwc3: gadget: Improve dwc3_gadget_suspend() and dwc3_gadget_resume()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/gadget.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index e0c67a256c214..2d5a4d0e63c61 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -3531,7 +3531,7 @@ static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
+                * streams are updated, and the device controller will not be
+                * triggered to generate ERDY to move the next stream data. To
+                * workaround this and maintain compatibility with various
+-               * hosts, force to reinitate the stream until the host is ready
++               * hosts, force to reinitiate the stream until the host is ready
+                * instead of waiting for the host to prime the endpoint.
+                */
+               if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
+@@ -4059,7 +4059,7 @@ static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
+       unsigned int is_ss = evtinfo & BIT(4);
+ 
+       /*
+-       * WORKAROUND: DWC3 revison 2.20a with hibernation support
++       * WORKAROUND: DWC3 revision 2.20a with hibernation support
+        * have a known issue which can cause USB CV TD.9.23 to fail
+        * randomly.
+        *
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-fix-use-after-free-on-core-driver-unbind.patch b/queue-5.15/usb-dwc3-fix-use-after-free-on-core-driver-unbind.patch
new file mode 100644 (file)
index 0000000..dbdca76
--- /dev/null
+++ b/queue-5.15/usb-dwc3-fix-use-after-free-on-core-driver-unbind.patch
@@ -0,0 +1,53 @@
+From 5b9830d5a1be5da704129fe6cb95fe5f36397745 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 12:05:40 +0200
+Subject: USB: dwc3: fix use-after-free on core driver unbind
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit e3dbb657571509044be15184a13134fa7c1fdca1 ]
+
+Some dwc3 glue drivers are currently accessing the driver data of the
+child core device directly, which is clearly a bad idea as the child may
+not have probed yet or may have been unbound from its driver.
+
+As a workaround until the glue drivers have been fixed, clear the driver
+data pointer before allowing the glue parent device to runtime suspend
+to prevent its driver from accessing data that has been freed during
+unbind.
+
+Fixes: 6dd2565989b4 ("usb: dwc3: add imx8mp dwc3 glue layer driver")
+Fixes: 6895ea55c385 ("usb: dwc3: qcom: Configure wakeup interrupts during suspend")
+Cc: stable@vger.kernel.org      # 5.12
+Cc: Li Jun <jun.li@nxp.com>
+Cc: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
+Cc: Krishna Kurapati <quic_kriskura@quicinc.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Message-ID: <20230607100540.31045-3-johan+linaro@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index ac119a88e6c76..6377b9cf81a59 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1719,6 +1719,11 @@ static int dwc3_remove(struct platform_device *pdev)
+       pm_runtime_allow(&pdev->dev);
+       pm_runtime_disable(&pdev->dev);
+       pm_runtime_put_noidle(&pdev->dev);
++      /*
++       * HACK: Clear the driver data, which is currently accessed by parent
++       * glue drivers, before allowing the parent to suspend.
++       */
++      platform_set_drvdata(pdev, NULL);
+       pm_runtime_set_suspended(&pdev->dev);
+ 
+       dwc3_free_event_buffers(dwc);
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-gadget-drop-dead-hibernation-code.patch b/queue-5.15/usb-dwc3-gadget-drop-dead-hibernation-code.patch
new file mode 100644 (file)
index 0000000..861a557
--- /dev/null
+++ b/queue-5.15/usb-dwc3-gadget-drop-dead-hibernation-code.patch
@@ -0,0 +1,141 @@
+From 9ccf38cdcaeb244187251377a9fe045149a7f452 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 4 Apr 2023 09:25:17 +0200
+Subject: USB: dwc3: gadget: drop dead hibernation code
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit bdb19d01026a5cccfa437be8adcf2df472c5889e ]
+
+The hibernation code is broken and has never been enabled in mainline
+and should thus be dropped.
+
+Remove the hibernation bits from the gadget code, which effectively
+reverts commits e1dadd3b0f27 ("usb: dwc3: workaround: bogus hibernation
+events") and 7b2a0368bbc9 ("usb: dwc3: gadget: set KEEP_CONNECT in case
+of hibernation") except for the spurious interrupt warning.
+
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20230404072524.19014-5-johan+linaro@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: c8540870af4c ("usb: dwc3: gadget: Improve dwc3_gadget_suspend() and dwc3_gadget_resume()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/gadget.c | 46 +++++----------------------------------
+ 1 file changed, 6 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index 2d5a4d0e63c61..a1be110f7ced1 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -2412,7 +2412,7 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
+       dwc3_writel(dwc->regs, DWC3_DCFG, reg);
+ }
+ 
+-static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
++static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
+ {
+       u32                     reg;
+       u32                     timeout = 500;
+@@ -2431,17 +2431,11 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
+                       reg &= ~DWC3_DCTL_KEEP_CONNECT;
+               reg |= DWC3_DCTL_RUN_STOP;
+ 
+-              if (dwc->has_hibernation)
+-                      reg |= DWC3_DCTL_KEEP_CONNECT;
+-
+               __dwc3_gadget_set_speed(dwc);
+               dwc->pullups_connected = true;
+       } else {
+               reg &= ~DWC3_DCTL_RUN_STOP;
+ 
+-              if (dwc->has_hibernation && !suspend)
+-                      reg &= ~DWC3_DCTL_KEEP_CONNECT;
+-
+               dwc->pullups_connected = false;
+       }
+ 
+@@ -2487,7 +2481,7 @@ static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
+        * remaining event generated by the controller while polling for
+        * DSTS.DEVCTLHLT.
+        */
+-      return dwc3_gadget_run_stop(dwc, false, false);
++      return dwc3_gadget_run_stop(dwc, false);
+ }
+ 
+ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+@@ -2555,7 +2549,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+ 
+               dwc3_event_buffers_setup(dwc);
+               __dwc3_gadget_start(dwc);
+-              ret = dwc3_gadget_run_stop(dwc, true, false);
++              ret = dwc3_gadget_run_stop(dwc, true);
+       }
+ 
+       pm_runtime_put(dwc->dev);
+@@ -4053,30 +4047,6 @@ static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
+       dwc->link_state = next;
+ }
+ 
+-static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
+-              unsigned int evtinfo)
+-{
+-      unsigned int is_ss = evtinfo & BIT(4);
+-
+-      /*
+-       * WORKAROUND: DWC3 revision 2.20a with hibernation support
+-       * have a known issue which can cause USB CV TD.9.23 to fail
+-       * randomly.
+-       *
+-       * Because of this issue, core could generate bogus hibernation
+-       * events which SW needs to ignore.
+-       *
+-       * Refers to:
+-       *
+-       * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
+-       * Device Fallback from SuperSpeed
+-       */
+-      if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
+-              return;
+-
+-      /* enter hibernation here */
+-}
+-
+ static void dwc3_gadget_interrupt(struct dwc3 *dwc,
+               const struct dwc3_event_devt *event)
+ {
+@@ -4094,11 +4064,7 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc,
+               dwc3_gadget_wakeup_interrupt(dwc);
+               break;
+       case DWC3_DEVICE_EVENT_HIBER_REQ:
+-              if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
+-                                      "unexpected hibernation event\n"))
+-                      break;
+-
+-              dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
++              dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
+               break;
+       case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
+               dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
+@@ -4444,7 +4410,7 @@ int dwc3_gadget_suspend(struct dwc3 *dwc)
+       if (!dwc->gadget_driver)
+               return 0;
+ 
+-      dwc3_gadget_run_stop(dwc, false, false);
++      dwc3_gadget_run_stop(dwc, false);
+ 
+       spin_lock_irqsave(&dwc->lock, flags);
+       dwc3_disconnect_gadget(dwc);
+@@ -4465,7 +4431,7 @@ int dwc3_gadget_resume(struct dwc3 *dwc)
+       if (ret < 0)
+               goto err0;
+ 
+-      ret = dwc3_gadget_run_stop(dwc, true, false);
++      ret = dwc3_gadget_run_stop(dwc, true);
+       if (ret < 0)
+               goto err1;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-gadget-improve-dwc3_gadget_suspend-and-dwc3.patch b/queue-5.15/usb-dwc3-gadget-improve-dwc3_gadget_suspend-and-dwc3.patch
new file mode 100644 (file)
index 0000000..4518f0d
--- /dev/null
+++ b/queue-5.15/usb-dwc3-gadget-improve-dwc3_gadget_suspend-and-dwc3.patch
@@ -0,0 +1,144 @@
+From 5b0377811a86ed846908a82235d971df3c0428fa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 May 2023 14:00:48 +0300
+Subject: usb: dwc3: gadget: Improve dwc3_gadget_suspend() and
+ dwc3_gadget_resume()
+
+From: Roger Quadros <rogerq@kernel.org>
+
+[ Upstream commit c8540870af4ce6ddeb27a7bb5498b75fb29b643c ]
+
+Prevent -ETIMEDOUT error on .suspend().
+e.g. If gadget driver is loaded and we are connected to a USB host,
+all transfers must be stopped before stopping the controller else
+we will not get a clean stop i.e. dwc3_gadget_run_stop() will take
+several seconds to complete and will return -ETIMEDOUT.
+
+Handle error cases properly in dwc3_gadget_suspend().
+Simplify dwc3_gadget_resume() by using the introduced helper function.
+
+Fixes: 9f8a67b65a49 ("usb: dwc3: gadget: fix gadget suspend/resume")
+Cc: stable@vger.kernel.org
+Suggested-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Signed-off-by: Roger Quadros <rogerq@kernel.org>
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Link: https://lore.kernel.org/r/20230503110048.30617-1-rogerq@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/gadget.c | 67 ++++++++++++++++++++-------------------
+ 1 file changed, 34 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index a1be110f7ced1..8ada601901cfa 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -2484,6 +2484,21 @@ static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
+       return dwc3_gadget_run_stop(dwc, false);
+ }
+ 
++static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
++{
++      /*
++       * In the Synopsys DWC_usb31 1.90a programming guide section
++       * 4.1.9, it specifies that for a reconnect after a
++       * device-initiated disconnect requires a core soft reset
++       * (DCTL.CSftRst) before enabling the run/stop bit.
++       */
++      dwc3_core_soft_reset(dwc);
++
++      dwc3_event_buffers_setup(dwc);
++      __dwc3_gadget_start(dwc);
++      return dwc3_gadget_run_stop(dwc, true);
++}
++
+ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+ {
+       struct dwc3             *dwc = gadget_to_dwc(g);
+@@ -2536,21 +2551,10 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+ 
+       synchronize_irq(dwc->irq_gadget);
+ 
+-      if (!is_on) {
++      if (!is_on)
+               ret = dwc3_gadget_soft_disconnect(dwc);
+-      } else {
+-              /*
+-               * In the Synopsys DWC_usb31 1.90a programming guide section
+-               * 4.1.9, it specifies that for a reconnect after a
+-               * device-initiated disconnect requires a core soft reset
+-               * (DCTL.CSftRst) before enabling the run/stop bit.
+-               */
+-              dwc3_core_soft_reset(dwc);
+-
+-              dwc3_event_buffers_setup(dwc);
+-              __dwc3_gadget_start(dwc);
+-              ret = dwc3_gadget_run_stop(dwc, true);
+-      }
++      else
++              ret = dwc3_gadget_soft_connect(dwc);
+ 
+       pm_runtime_put(dwc->dev);
+ 
+@@ -4406,42 +4410,39 @@ void dwc3_gadget_exit(struct dwc3 *dwc)
+ int dwc3_gadget_suspend(struct dwc3 *dwc)
+ {
+       unsigned long flags;
++      int ret;
+ 
+       if (!dwc->gadget_driver)
+               return 0;
+ 
+-      dwc3_gadget_run_stop(dwc, false);
++      ret = dwc3_gadget_soft_disconnect(dwc);
++      if (ret)
++              goto err;
+ 
+       spin_lock_irqsave(&dwc->lock, flags);
+       dwc3_disconnect_gadget(dwc);
+-      __dwc3_gadget_stop(dwc);
+       spin_unlock_irqrestore(&dwc->lock, flags);
+ 
+       return 0;
++
++err:
++      /*
++       * Attempt to reset the controller's state. Likely no
++       * communication can be established until the host
++       * performs a port reset.
++       */
++      if (dwc->softconnect)
++              dwc3_gadget_soft_connect(dwc);
++
++      return ret;
+ }
+ 
+ int dwc3_gadget_resume(struct dwc3 *dwc)
+ {
+-      int                     ret;
+-
+       if (!dwc->gadget_driver || !dwc->softconnect)
+               return 0;
+ 
+-      ret = __dwc3_gadget_start(dwc);
+-      if (ret < 0)
+-              goto err0;
+-
+-      ret = dwc3_gadget_run_stop(dwc, true);
+-      if (ret < 0)
+-              goto err1;
+-
+-      return 0;
+-
+-err1:
+-      __dwc3_gadget_stop(dwc);
+-
+-err0:
+-      return ret;
++      return dwc3_gadget_soft_connect(dwc);
+ }
+ 
+ void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-gadget-synchronize-irq-between-soft-connect.patch b/queue-5.15/usb-dwc3-gadget-synchronize-irq-between-soft-connect.patch
new file mode 100644 (file)
index 0000000..5788f05
--- /dev/null
+++ b/queue-5.15/usb-dwc3-gadget-synchronize-irq-between-soft-connect.patch
@@ -0,0 +1,40 @@
+From 2b95a403609277b4821531916cd8e5a8c2c57917 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Aug 2022 11:23:53 -0700
+Subject: usb: dwc3: gadget: Synchronize IRQ between soft connect/disconnect
+
+From: Wesley Cheng <quic_wcheng@quicinc.com>
+
+[ Upstream commit 9711c67de7482c81e1daca3548fbc5c9603600e3 ]
+
+Ensure that there are no pending events being handled in between soft
+connect/disconnect transitions.  As we are keeping interrupts enabled,
+and EP0 events are still being serviced, this avoids any stale events from
+being serviced.
+
+Reviewed-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
+Link: https://lore.kernel.org/r/20220817182359.13550-4-quic_wcheng@quicinc.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: c8540870af4c ("usb: dwc3: gadget: Improve dwc3_gadget_suspend() and dwc3_gadget_resume()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/gadget.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index d76a4837615d9..b2ffc98c9e747 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -2540,6 +2540,8 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+               return 0;
+       }
+ 
++      synchronize_irq(dwc->irq_gadget);
++
+       if (!is_on) {
+               ret = dwc3_gadget_soft_disconnect(dwc);
+       } else {
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-qcom-fix-null-deref-on-suspend.patch b/queue-5.15/usb-dwc3-qcom-fix-null-deref-on-suspend.patch
new file mode 100644 (file)
index 0000000..f995400
--- /dev/null
+++ b/queue-5.15/usb-dwc3-qcom-fix-null-deref-on-suspend.patch
@@ -0,0 +1,68 @@
+From 4db5be58058e990a68bf41ca436ae6688d7c57b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 12:05:39 +0200
+Subject: USB: dwc3: qcom: fix NULL-deref on suspend
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit d2d69354226de0b333d4405981f3d9c41ba8430a ]
+
+The Qualcomm dwc3 glue driver is currently accessing the driver data of
+the child core device during suspend and on wakeup interrupts. This is
+clearly a bad idea as the child may not have probed yet or could have
+been unbound from its driver.
+
+The first such layering violation was part of the initial version of the
+driver, but this was later made worse when the hack that accesses the
+driver data of the grand child xhci device to configure the wakeup
+interrupts was added.
+
+Fixing this properly is not that easily done, so add a sanity check to
+make sure that the child driver data is non-NULL before dereferencing it
+for now.
+
+Note that this relies on subtleties like the fact that driver core is
+making sure that the parent is not suspended while the child is probing.
+
+Reported-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/all/20230325165217.31069-4-manivannan.sadhasivam@linaro.org/
+Fixes: d9152161b4bf ("usb: dwc3: Add Qualcomm DWC3 glue layer driver")
+Fixes: 6895ea55c385 ("usb: dwc3: qcom: Configure wakeup interrupts during suspend")
+Cc: stable@vger.kernel.org     # 3.18: a872ab303d5d: "usb: dwc3: qcom: fix use-after-free on runtime-PM wakeup"
+Cc: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
+Cc: Krishna Kurapati <quic_kriskura@quicinc.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Message-ID: <20230607100540.31045-2-johan+linaro@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/dwc3-qcom.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
+index 73c0c381e5d05..0180350a2c95c 100644
+--- a/drivers/usb/dwc3/dwc3-qcom.c
++++ b/drivers/usb/dwc3/dwc3-qcom.c
+@@ -306,7 +306,16 @@ static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
+ /* Only usable in contexts where the role can not change. */
+ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
+ {
+-      struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
++      struct dwc3 *dwc;
++
++      /*
++       * FIXME: Fix this layering violation.
++       */
++      dwc = platform_get_drvdata(qcom->dwc3);
++
++      /* Core driver may not have probed yet. */
++      if (!dwc)
++              return false;
+ 
+       return dwc->xhci;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-dwc3-remove-dwc3-locking-during-gadget-suspend-r.patch b/queue-5.15/usb-dwc3-remove-dwc3-locking-during-gadget-suspend-r.patch
new file mode 100644 (file)
index 0000000..6cfbab4
--- /dev/null
+++ b/queue-5.15/usb-dwc3-remove-dwc3-locking-during-gadget-suspend-r.patch
@@ -0,0 +1,72 @@
+From f3a553691873bac969d5d35cf2e655b9a51a9fd5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 12:36:22 -0700
+Subject: usb: dwc3: Remove DWC3 locking during gadget suspend/resume
+
+From: Wesley Cheng <quic_wcheng@quicinc.com>
+
+[ Upstream commit 5265397f94424eaea596026fd34dc7acf474dcec ]
+
+Remove the need for making dwc3_gadget_suspend() and dwc3_gadget_resume()
+to be called in a spinlock, as dwc3_gadget_run_stop() could potentially
+take some time to complete.
+
+Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
+Link: https://lore.kernel.org/r/20220901193625.8727-3-quic_wcheng@quicinc.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: c8540870af4c ("usb: dwc3: gadget: Improve dwc3_gadget_suspend() and dwc3_gadget_resume()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/core.c   | 4 ----
+ drivers/usb/dwc3/gadget.c | 5 +++++
+ 2 files changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index f2e841bc05c70..ac119a88e6c76 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1766,9 +1766,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
+       case DWC3_GCTL_PRTCAP_DEVICE:
+               if (pm_runtime_suspended(dwc->dev))
+                       break;
+-              spin_lock_irqsave(&dwc->lock, flags);
+               dwc3_gadget_suspend(dwc);
+-              spin_unlock_irqrestore(&dwc->lock, flags);
+               synchronize_irq(dwc->irq_gadget);
+               dwc3_core_exit(dwc);
+               break;
+@@ -1829,9 +1827,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
+                       return ret;
+ 
+               dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
+-              spin_lock_irqsave(&dwc->lock, flags);
+               dwc3_gadget_resume(dwc);
+-              spin_unlock_irqrestore(&dwc->lock, flags);
+               break;
+       case DWC3_GCTL_PRTCAP_HOST:
+               if (!PMSG_IS_AUTO(msg)) {
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index b2ffc98c9e747..e0c67a256c214 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -4439,12 +4439,17 @@ void dwc3_gadget_exit(struct dwc3 *dwc)
+ 
+ int dwc3_gadget_suspend(struct dwc3 *dwc)
+ {
++      unsigned long flags;
++
+       if (!dwc->gadget_driver)
+               return 0;
+ 
+       dwc3_gadget_run_stop(dwc, false, false);
++
++      spin_lock_irqsave(&dwc->lock, flags);
+       dwc3_disconnect_gadget(dwc);
+       __dwc3_gadget_stop(dwc);
++      spin_unlock_irqrestore(&dwc->lock, flags);
+ 
+       return 0;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.15/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch b/queue-5.15/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
new file mode 100644 (file)
index 0000000..2205cf7
--- /dev/null
+++ b/queue-5.15/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
@@ -0,0 +1,61 @@
+From 24b9b04dfa70e9dbf0a5dc653b03a824f35747ff Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 9 May 2023 18:57:52 +0530
+Subject: usb: gadget: u_serial: Avoid spinlock recursion in __gs_console_push
+
+From: Prashanth K <quic_prashk@quicinc.com>
+
+[ Upstream commit e5990469943c711cb00bfde6338d2add6c6d0bfe ]
+
+When serial console over USB is enabled, gs_console_connect
+queues gs_console_work, where it acquires the spinlock and
+queues the usb request, and this request goes to gadget layer.
+Now consider a situation where gadget layer prints something
+to dmesg, this will eventually call gs_console_write() which
+requires cons->lock. And this causes spinlock recursion. Avoid
+this by excluding usb_ep_queue from the spinlock.
+
+ spin_lock_irqsave //needs cons->lock
+ gs_console_write
+       .
+       .
+ _printk
+ __warn_printk
+ dev_warn/pr_err
+       .
+       .
+ [USB Gadget Layer]
+       .
+       .
+ usb_ep_queue
+ gs_console_work
+ __gs_console_push // acquires cons->lock
+ process_one_work
+
+Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
+Link: https://lore.kernel.org/r/1683638872-6885-1-git-send-email-quic_prashk@quicinc.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/gadget/function/u_serial.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
+index a8d1e8b192c55..f975dc03a1904 100644
+--- a/drivers/usb/gadget/function/u_serial.c
++++ b/drivers/usb/gadget/function/u_serial.c
+@@ -915,8 +915,11 @@ static void __gs_console_push(struct gs_console *cons)
+       }
+ 
+       req->length = size;
++
++      spin_unlock_irq(&cons->lock);
+       if (usb_ep_queue(ep, req, GFP_ATOMIC))
+               req->length = 0;
++      spin_lock_irq(&cons->lock);
+ }
+ 
+ static void gs_console_work(struct work_struct *work)
+-- 
+2.40.1
+

diff --git a/queue-5.15/watchdog-sp5100_tco-support-hygon-fch-sch-server-con.patch b/queue-5.15/watchdog-sp5100_tco-support-hygon-fch-sch-server-con.patch
new file mode 100644 (file)
index 0000000..0199b82
--- /dev/null
+++ b/queue-5.15/watchdog-sp5100_tco-support-hygon-fch-sch-server-con.patch
@@ -0,0 +1,46 @@
+From 972de6e9fa7b7c204b6a97c368df6739b3310e4d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Jun 2023 11:19:07 +0800
+Subject: watchdog: sp5100_tco: support Hygon FCH/SCH (Server Controller Hub)
+
+From: Yuechao Zhao <yuechao.zhao@advantech.com.cn>
+
+[ Upstream commit 009637de1f65cff452ad49554d1e8ef9fda99e43 ]
+
+Add PCI_VENDOR_ID_HYGON(Hygon vendor id [0x1d94]) in this driver
+
+Signed-off-by: Yuechao Zhao <yuechao.zhao@advantech.com.cn>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lkml.kernel.org/r/20230612031907.796461-1-a345351830@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/watchdog/sp5100_tco.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c
+index 1e327fb1ad202..0141858188c56 100644
+--- a/drivers/watchdog/sp5100_tco.c
++++ b/drivers/watchdog/sp5100_tco.c
+@@ -89,7 +89,7 @@ static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
+           sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
+           sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
+               return efch_mmio;
+-      } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
++      } else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
+           ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
+            dev->revision >= 0x41) ||
+           (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
+@@ -561,6 +561,8 @@ static const struct pci_device_id sp5100_tco_pci_tbl[] = {
+         PCI_ANY_ID, },
+       { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
+         PCI_ANY_ID, },
++      { PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
++        PCI_ANY_ID, },
+       { 0, },                 /* End of list */
+ };
+ MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
+-- 
+2.40.1
+

diff --git a/queue-5.15/xsk-add-cb-area-to-struct-xdp_buff_xsk.patch b/queue-5.15/xsk-add-cb-area-to-struct-xdp_buff_xsk.patch
new file mode 100644 (file)
index 0000000..cd37389
--- /dev/null
+++ b/queue-5.15/xsk-add-cb-area-to-struct-xdp_buff_xsk.patch
@@ -0,0 +1,69 @@
+From 65bf169438f4b555b96d411bdc60832ff3c33414 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 19 Jan 2023 14:15:33 -0800
+Subject: xsk: Add cb area to struct xdp_buff_xsk
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Toke Høiland-Jørgensen <toke@redhat.com>
+
+[ Upstream commit 94ecc5ca4dbf1f01bae6e32f5cd88c0fc5dc3cc9 ]
+
+Add an area after the xdp_buff in struct xdp_buff_xsk that drivers can use
+to stash extra information to use in metadata kfuncs. The maximum size of
+24 bytes means the full xdp_buff_xsk structure will take up exactly two
+cache lines (with the cb field spanning both). Also add a macro drivers can
+use to check their own wrapping structs against the available size.
+
+Cc: John Fastabend <john.fastabend@gmail.com>
+Cc: David Ahern <dsahern@gmail.com>
+Cc: Martin KaFai Lau <martin.lau@linux.dev>
+Cc: Jakub Kicinski <kuba@kernel.org>
+Cc: Willem de Bruijn <willemb@google.com>
+Cc: Jesper Dangaard Brouer <brouer@redhat.com>
+Cc: Anatoly Burakov <anatoly.burakov@intel.com>
+Cc: Alexander Lobakin <alexandr.lobakin@intel.com>
+Cc: Magnus Karlsson <magnus.karlsson@gmail.com>
+Cc: Maryam Tahhan <mtahhan@redhat.com>
+Cc: xdp-hints@xdp-project.net
+Cc: netdev@vger.kernel.org
+Suggested-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Toke Høiland-Jørgensen <toke@redhat.com>
+Signed-off-by: Stanislav Fomichev <sdf@google.com>
+Link: https://lore.kernel.org/r/20230119221536.3349901-15-sdf@google.com
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Stable-dep-of: 3ce29c17dc84 ("igc: read before write to SRRCTL register")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/net/xsk_buff_pool.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/include/net/xsk_buff_pool.h b/include/net/xsk_buff_pool.h
+index ebd1f43578d65..14db77ff5fca5 100644
+--- a/include/net/xsk_buff_pool.h
++++ b/include/net/xsk_buff_pool.h
+@@ -18,8 +18,11 @@ struct xdp_sock;
+ struct device;
+ struct page;
+ 
++#define XSK_PRIV_MAX 24
++
+ struct xdp_buff_xsk {
+       struct xdp_buff xdp;
++      u8 cb[XSK_PRIV_MAX];
+       dma_addr_t dma;
+       dma_addr_t frame_dma;
+       struct xsk_buff_pool *pool;
+@@ -28,6 +31,8 @@ struct xdp_buff_xsk {
+       struct list_head free_list_node;
+ };
+ 
++#define XSK_CHECK_PRIV_TYPE(t) BUILD_BUG_ON(sizeof(t) > offsetofend(struct xdp_buff_xsk, cb))
++
+ struct xsk_dma_map {
+       dma_addr_t *dma_pages;
+       struct device *dev;
+-- 
+2.40.1
+