powerpc/e500: remove enc and ind fields from struct mmu_psize_def

enc field is hidden behind BOOK3E_PAGESZ_XX macros, and when you look
closer you realise that this field is nothing else than the value of shift
minus ten.

So remove enc field and calculate tsize from shift field.

Also remove inc field which is unused.

Link: https://lkml.kernel.org/r/e99136779b5b0829c2c60d37f305a1410c65cf9b.1719928057.git.christophe.leroy@csgroup.eu
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Oscar Salvador <osalvador@suse.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Peter Xu <peterx@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>

diff --git a/arch/powerpc/include/asm/nohash/mmu-e500.h b/arch/powerpc/include/asm/nohash/mmu-e500.h
index 7dc24b8632d7c2abde907af455e8559fac219708..b281d9eeaf1e651e8e59ce3f90c1c6fb5eda83c0 100644 (file)
--- a/arch/powerpc/include/asm/nohash/mmu-e500.h
+++ b/arch/powerpc/include/asm/nohash/mmu-e500.h
@@ -244,14 +244,11 @@ typedef struct {
 /* Page size definitions, common between 32 and 64-bit
  *
  *    shift : is the "PAGE_SHIFT" value for that page size
- *    penc  : is the pte encoding mask
  *
  */
 struct mmu_psize_def
 {
        unsigned int    shift;  /* number of bits */
-       unsigned int    enc;    /* PTE encoding */
-       unsigned int    ind;    /* Corresponding indirect page size shift */
        unsigned int    flags;
 #define MMU_PAGE_SIZE_DIRECT   0x1     /* Supported as a direct size */
 #define MMU_PAGE_SIZE_INDIRECT 0x2     /* Supported as an indirect size */

diff --git a/arch/powerpc/mm/nohash/book3e_pgtable.c b/arch/powerpc/mm/nohash/book3e_pgtable.c
index 1c5e4ecbebebf1bbccdaf66232e26f6db926a572..ad2a7c26f2a00ba9844ea8222e054b9bd6e94ecf 100644 (file)
--- a/arch/powerpc/mm/nohash/book3e_pgtable.c
+++ b/arch/powerpc/mm/nohash/book3e_pgtable.c
@@ -29,10 +29,10 @@ int __meminit vmemmap_create_mapping(unsigned long start,
                _PAGE_KERNEL_RW;
 
        /* PTEs only contain page size encodings up to 32M */
-       BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].enc > 0xf);
+       BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].shift - 10 > 0xf);
 
        /* Encode the size in the PTE */
-       flags |= mmu_psize_defs[mmu_vmemmap_psize].enc << 8;
+       flags |= (mmu_psize_defs[mmu_vmemmap_psize].shift - 10) << 8;
 
        /* For each PTE for that area, map things. Note that we don't
         * increment phys because all PTEs are of the large size and

diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c
index f57dc721d0636a7d27cb3ab5f8e703dc1c2062b0..b653a7be4cb1d3950c39b9a8c955ebd1d80e7ee6 100644 (file)
--- a/arch/powerpc/mm/nohash/tlb.c
+++ b/arch/powerpc/mm/nohash/tlb.c
@@ -53,37 +53,30 @@
 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
        [MMU_PAGE_4K] = {
                .shift  = 12,
-               .enc    = BOOK3E_PAGESZ_4K,
        },
        [MMU_PAGE_2M] = {
                .shift  = 21,
-               .enc    = BOOK3E_PAGESZ_2M,
        },
        [MMU_PAGE_4M] = {
                .shift  = 22,
-               .enc    = BOOK3E_PAGESZ_4M,
        },
        [MMU_PAGE_16M] = {
                .shift  = 24,
-               .enc    = BOOK3E_PAGESZ_16M,
        },
        [MMU_PAGE_64M] = {
                .shift  = 26,
-               .enc    = BOOK3E_PAGESZ_64M,
        },
        [MMU_PAGE_256M] = {
                .shift  = 28,
-               .enc    = BOOK3E_PAGESZ_256M,
        },
        [MMU_PAGE_1G] = {
                .shift  = 30,
-               .enc    = BOOK3E_PAGESZ_1GB,
        },
 };
 
 static inline int mmu_get_tsize(int psize)
 {
-       return mmu_psize_defs[psize].enc;
+       return mmu_psize_defs[psize].shift - 10;
 }
 #else
 static inline int mmu_get_tsize(int psize)

diff --git a/arch/powerpc/mm/nohash/tlb_64e.c b/arch/powerpc/mm/nohash/tlb_64e.c
index 0eb1e8d99c6d93b9d3a9aba08b2baf14166d18be..113edf76d3ce4494a94e53c0fca672a00a6a86b4 100644 (file)
--- a/arch/powerpc/mm/nohash/tlb_64e.c
+++ b/arch/powerpc/mm/nohash/tlb_64e.c
@@ -53,7 +53,7 @@ int extlb_level_exc;
  */
 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
 {
-       int tsize = mmu_psize_defs[mmu_pte_psize].enc;
+       int tsize = mmu_psize_defs[mmu_pte_psize].shift - 10;
 
        if (book3e_htw_mode != PPC_HTW_NONE) {
                unsigned long start = address & PMD_MASK;