riscv: hwprobe: Expose Zicbop extension and its block size

- Add `RISCV_HWPROBE_EXT_ZICBOP` to report the presence of the
  Zicbop extension.
- Add `RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE` to expose the block
  size (in bytes) when Zicbop is supported.
- Update hwprobe.rst to document the new extension bit and block
  size key, following the existing Zicbom/Zicboz style.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
Link: https://patch.msgid.link/20251118162436.15485-2-zihong.plct@isrc.iscas.ac.cn
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 8b36eaa9d5d8aaae46506d38649050bbaa64e67f..06c5280b728a27dd5370e29d31384d720e7f0ddf 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -278,6 +278,9 @@ The following keys are defined:
        ratified in commit 49f49c842ff9 ("Update to Rafified state") of
        riscv-zabha.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
+       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
@@ -373,3 +376,6 @@ The following keys are defined:
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
         vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
        Instruction Extensions Specification.
+
+* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
+  represents the size of the Zicbop block in bytes.

diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 58f8dda73259a8f6e729252ac68fef1db5a820e7..8c572a46471902826e51ac488e8b2273cc29d5a2 100644 (file)
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 14
+#define RISCV_HWPROBE_MAX_KEY 15
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 906896780999e6ac3a02883d55dca56c03686427..1edea2331b8bda8307adb95ba515249367c6a122 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -83,6 +83,7 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZALRSC        (1ULL << 57)
 #define                RISCV_HWPROBE_EXT_ZABHA         (1ULL << 58)
 #define                RISCV_HWPROBE_EXT_ZALASR        (1ULL << 59)
+#define                RISCV_HWPROBE_EXT_ZICBOP        (1ULL << 60)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
@@ -108,6 +109,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE    12
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0  13
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0    14
+#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE    15
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 55004d81631a19da2bf81eeef111f6f54ed91cbb..0f701ace3bb9a09f2ffd26e7e2da8dd7d68b7c6f 100644 (file)
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -123,6 +123,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZCB);
                EXT_KEY(ZCMOP);
                EXT_KEY(ZICBOM);
+               EXT_KEY(ZICBOP);
                EXT_KEY(ZICBOZ);
                EXT_KEY(ZICNTR);
                EXT_KEY(ZICOND);
@@ -303,6 +304,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
                if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
                        pair->value = riscv_cbom_block_size;
                break;
+       case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE:
+               pair->value = 0;
+               if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP))
+                       pair->value = riscv_cbop_block_size;
+               break;
        case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
                pair->value = user_max_virt_addr();
                break;