--- /dev/null
+From 6ed0dc3fd39558f48119daf8f99f835deb7d68da Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Tue, 18 Mar 2025 18:05:05 -0400
+Subject: drm/amd/display: Default IPS to RCG_IN_ACTIVE_IPS2_IN_OFF
+
+From: Leo Li <sunpeng.li@amd.com>
+
+commit 6ed0dc3fd39558f48119daf8f99f835deb7d68da upstream.
+
+[Why]
+
+Recent findings show negligible power savings between IPS2 and RCG
+during static desktop. In fact, DCN related clocks are higher
+when IPS2 is enabled vs RCG.
+
+RCG_IN_ACTIVE is also the default policy for another OS supported by
+DC, and it has faster entry/exit.
+
+[How]
+
+Remove previous logic that checked for IPS2 support, and just default
+to `DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF`.
+
+Fixes: 199888aa25b3 ("drm/amd/display: Update IPS default mode for DCN35/DCN351")
+Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
+Tested-by: Mark Broadworth <mark.broadworth@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 8f772d79ef39b463ead00ef6f009bebada3a9d49)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 --------------------
+ 1 file changed, 20 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1912,26 +1912,6 @@ static enum dmub_ips_disable_type dm_get
+
+ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+ case IP_VERSION(3, 5, 0):
+- /*
+- * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
+- * cause a hard hang. A fix exists for newer PMFW.
+- *
+- * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
+- * IPS state in all cases, except for s0ix and all displays off (DPMS),
+- * where IPS2 is allowed.
+- *
+- * When checking pmfw version, use the major and minor only.
+- */
+- if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
+- ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+- else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))
+- /*
+- * Other ASICs with DCN35 that have residency issues with
+- * IPS2 in idle.
+- * We want them to use IPS2 only in display off cases.
+- */
+- ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+- break;
+ case IP_VERSION(3, 5, 1):
+ ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+ break;