can be safely mapped as cacheable. This relies on the presence of
force write back (FWB) feature support on the hardware.
-7.45 KVM_CAP_S390_USER_OPEREXEC
+7.45 KVM_CAP_ARM_SEA_TO_USER
+----------------------------
+
+:Architecture: arm64
+:Target: VM
+:Parameters: none
+:Returns: 0 on success, -EINVAL if unsupported.
+
+When this capability is enabled, KVM may exit to userspace for SEAs taken to
+EL2 resulting from a guest access. See ``KVM_EXIT_ARM_SEA`` for more
+information.
+
++7.46 KVM_CAP_S390_USER_OPEREXEC
+ -------------------------------
+
+ :Architectures: s390
+ :Parameters: none
+
+ When this capability is enabled KVM forwards all operation exceptions
+ that it doesn't handle itself to user space. This also includes the
+ 0x0000 instructions managed by KVM_CAP_S390_USER_INSTR0. This is
+ helpful if user space wants to emulate instructions which are not
+ (yet) implemented in hardware.
+
+ This capability can be enabled dynamically even if VCPUs were already
+ created and are running.
+
8. Other capabilities.
======================
#define KVM_CAP_RISCV_MP_STATE_RESET 242
#define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 243
#define KVM_CAP_GUEST_MEMFD_FLAGS 244
-#define KVM_CAP_S390_USER_OPEREXEC 245
+#define KVM_CAP_ARM_SEA_TO_USER 245
++#define KVM_CAP_S390_USER_OPEREXEC 246
struct kvm_irq_routing_irqchip {
__u32 irqchip;