RISC-V: Adapt VLS init tests

Realize that init tests are wrong by my previous mistakes.
Fix them and committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Fix init test.
	* gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2e91b9a9664adc54732cac40cfe319cadf5ef47d..9cc3656e710e155d6c62cd3debe5c7764d7f8924 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -437,7 +437,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
   void init_##TYPE1##_##TYPE2##_##NUM (VARS##NUM (TYPE2, __VA_ARGS__),         \
                                       TYPE2 *__restrict out)                  \
   {                                                                            \
-    TYPE1 v = {INIT##NUM (__VA_ARGS__)};                                       \
+    TYPE1 v = {__VA_ARGS__};                                                   \
     *(TYPE1 *) out = v;                                                        \
   }
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
index aec2c6e5e5fb367dd653c141ebadeb51e066c94a..0f78ae0ebe266bd9545542a985d973d27c6faee1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
@@ -43,4 +43,4 @@ DEF_INIT (v128uqi, uint8_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
          113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
          127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
index f9c58aef5538ba4af3438df32cbcea62f86b5369..f27c395441b25adb135688cc07e510f4083789bd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
@@ -45,4 +45,4 @@ DEF_INIT (v128uhi, uint16_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
          113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
          127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.vx} 494 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
index eb970c7b042f25fb22e293df5f9d919609683fd6..df15bd7300f406cd4cff8158587a377bbe73f201 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
@@ -24,4 +24,4 @@ DEF_INIT (v128hf, _Float16, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
          113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
          127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle16\.v} 7 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
index fedeb445a2bede58dd48d1169b86e9c34c489f3c..09bdbd19cc00c03ceca817b2492b7f86a25417b7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
@@ -45,4 +45,4 @@ DEF_INIT (v128usi, uint32_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
          113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
          127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
index c93ac524c880b6cf75c5b1b31ffa0c6db48d44af..65ca8cb41e364935166faa1165e273d5e03215fe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
@@ -23,4 +23,4 @@ DEF_INIT (v128sf, float, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
          100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
          114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle32\.v} 7 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
index 304539f486868c1620ac2ccb82afd9ef5c937151..9cd36ce2ec1170725de8c2a10ee8ceb1df52f9f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
@@ -45,4 +45,4 @@ DEF_INIT (v128udi, uint64_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
          113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
          127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
index 4b966010dca2fd0d5a2980be8e3fbb463c307cb1..ad337054f3ac3d5ffb51502068aa4345874e4f13 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
@@ -23,4 +23,4 @@ DEF_INIT (v128df, double, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
          100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
          114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle64\.v} 7 } } */