clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider

While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured and select the rate based on the opp table and the source will
be changed to APSS_PLL_EARLY.

Without this patch, CPU Freq driver reports that CPU is running at 24MHz
instead of the 800MHz.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index 0783d1aa8efa354556ee56f63b0c887b423fe523..e6295b832686cd7daa5ea70c79f31c2ad09fde2f 100644 (file)
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -23,16 +23,19 @@
 
 enum {
        P_XO,
+       P_GPLL0,
        P_APSS_PLL_EARLY,
 };
 
 static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
        { .fw_name = "xo" },
+       { .fw_name = "gpll0" },
        { .fw_name = "pll" },
 };
 
 static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
        { P_XO, 0 },
+       { P_GPLL0, 4 },
        { P_APSS_PLL_EARLY, 5 },
 };