3.0-stable patches

added patches:
	arm-7296-1-proc-v7.s-remove-harvard_cache-preprocessor-guards.patch
	mach-ux500-enable-arm-errata-764369.patch

diff --git a/queue-3.0/arm-7296-1-proc-v7.s-remove-harvard_cache-preprocessor-guards.patch b/queue-3.0/arm-7296-1-proc-v7.s-remove-harvard_cache-preprocessor-guards.patch
new file mode 100644 (file)
index 0000000..f9a6486
--- /dev/null
+++ b/queue-3.0/arm-7296-1-proc-v7.s-remove-harvard_cache-preprocessor-guards.patch
@@ -0,0 +1,50 @@
+From 612539e81f655f6ac73c7af1da8701c1ee618aee Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Fri, 20 Jan 2012 12:10:18 +0100
+Subject: ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 612539e81f655f6ac73c7af1da8701c1ee618aee upstream.
+
+On v7, we use the same cache maintenance instructions for data lines
+as for unified lines. This was not the case for v6, where HARVARD_CACHE
+was defined to indicate the L1 cache topology.
+
+This patch removes the erroneous compile-time check for HARVARD_CACHE in
+proc-v7.S, ensuring that we perform I-side invalidation at boot.
+
+Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
+
+Acked-by: Catalin Marinas <Catalin.Marinas@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/mm/proc-v7.S |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/arch/arm/mm/proc-v7.S
++++ b/arch/arm/mm/proc-v7.S
+@@ -270,10 +270,6 @@ cpu_resume_l1_flags:
+  *    Initialise TLB, Caches, and MMU state ready to switch the MMU
+  *    on.  Return in r0 the new CP15 C1 control register setting.
+  *
+- *    We automatically detect if we have a Harvard cache, and use the
+- *    Harvard cache control instructions insead of the unified cache
+- *    control instructions.
+- *
+  *    This should be able to cover all ARMv7 cores.
+  *
+  *    It is assumed that:
+@@ -363,9 +359,7 @@ __v7_setup:
+ #endif
+ 
+ 3:    mov     r10, #0
+-#ifdef HARVARD_CACHE
+       mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
+-#endif
+       dsb
+ #ifdef CONFIG_MMU
+       mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs

diff --git a/queue-3.0/mach-ux500-enable-arm-errata-764369.patch b/queue-3.0/mach-ux500-enable-arm-errata-764369.patch
new file mode 100644 (file)
index 0000000..78be051
--- /dev/null
+++ b/queue-3.0/mach-ux500-enable-arm-errata-764369.patch
@@ -0,0 +1,29 @@
+From d65015f7c5c5be9fd3f5e567889c844ba81bdc9c Mon Sep 17 00:00:00 2001
+From: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+Date: Thu, 12 Jan 2012 11:07:43 +0530
+Subject: mach-ux500: enable ARM errata 764369
+
+From: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+
+commit d65015f7c5c5be9fd3f5e567889c844ba81bdc9c upstream.
+
+This applies ARM errata 764369 for all ux500 platforms.
+
+Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/mach-ux500/Kconfig |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-ux500/Kconfig
++++ b/arch/arm/mach-ux500/Kconfig
+@@ -7,6 +7,7 @@ config UX500_SOC_COMMON
+       select HAS_MTU
+       select ARM_ERRATA_753970
+       select ARM_ERRATA_754322
++      select ARM_ERRATA_764369
+ 
+ menu "Ux500 SoC"
+ 

diff --git a/queue-3.0/series b/queue-3.0/series
index 43f3ac7cdd92af18561315f89fe714fef8737f5a..a02a69d7db98415c52ad3d93dc1684030de44110 100644 (file)
--- a/queue-3.0/series
+++ b/queue-3.0/series
@@ -20,3 +20,5 @@ alsa-hda-fix-silent-output-on-asus-a6rp.patch
 alsa-hda-fix-silent-output-on-haier-w18-laptop.patch
 drm-i915-sdvo-always-set-positive-sync-polarity.patch
 cap_syslog-don-t-use-warn_once-for-cap_sys_admin.patch
+mach-ux500-enable-arm-errata-764369.patch
+arm-7296-1-proc-v7.s-remove-harvard_cache-preprocessor-guards.patch