drm/amdgpu: Convert update_supported_modes into a common helper

So it can be used for future products

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index a073718cd2f633e3e722f8e13a0df6c2393450d6..9985eeab86768b74586ce7425fcb2e99ddd5cc50 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -597,6 +597,43 @@ int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev)
        return amdgpu_xcp_sched_list_update(adev);
 }
 
+void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)
+{
+       struct amdgpu_device *adev = xcp_mgr->adev;
+
+       xcp_mgr->supp_xcp_modes = 0;
+
+       switch (NUM_XCC(adev->gfx.xcc_mask)) {
+       case 8:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_QPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 6:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_TPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 4:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 2:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 1:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+
+       default:
+               break;
+       }
+}
+
 /*====================== xcp sysfs - configuration ======================*/
 #define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name)                         \
        static ssize_t amdgpu_xcp_res_sysfs_##_name##_show(        \

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 8b567ad7cce178d69a876ea5f12d263e6f9db36a..80996ea1be625f9428b4d0e1d2791f649fe7ccd2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -177,6 +177,7 @@ int amdgpu_xcp_select_scheds(struct amdgpu_device *adev,
                             struct amdgpu_fpriv *fpriv,
                             unsigned int *num_scheds,
                             struct drm_gpu_scheduler ***scheds);
+void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr);
 int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev);
 void amdgpu_xcp_sysfs_init(struct amdgpu_device *adev);
 void amdgpu_xcp_sysfs_fini(struct amdgpu_device *adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 6018a05973933b87000434222f3f95305374dea9..cc78af40512f175a65290684dbfd6b91fc6240e0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -396,45 +396,6 @@ static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr,
        return ret;
 }
 
-static void
-__aqua_vanjaram_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)
-{
-       struct amdgpu_device *adev = xcp_mgr->adev;
-
-       xcp_mgr->supp_xcp_modes = 0;
-
-       switch (NUM_XCC(adev->gfx.xcc_mask)) {
-       case 8:
-               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_QPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_CPX_PARTITION_MODE);
-               break;
-       case 6:
-               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_TPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_CPX_PARTITION_MODE);
-               break;
-       case 4:
-               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_CPX_PARTITION_MODE);
-               break;
-       /* this seems only existing in emulation phase */
-       case 2:
-               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_CPX_PARTITION_MODE);
-               break;
-       case 1:
-               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
-                                         BIT(AMDGPU_CPX_PARTITION_MODE);
-               break;
-
-       default:
-               break;
-       }
-}
-
 static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)
 {
        int mode;
@@ -591,7 +552,7 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
        if (ret)
                return ret;
 
-       __aqua_vanjaram_update_supported_modes(adev->xcp_mgr);
+       amdgpu_xcp_update_supported_modes(adev->xcp_mgr);
        /* TODO: Default memory node affinity init */
 
        return ret;