clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset

To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.

Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.

Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
index 9633d4506891213a51978fc4a15c268a06be3bdf..c80ac2dfbb60c3212d6f75ffd84221b1f73546d4 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
@@ -1371,7 +1371,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev)
 
        /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
        val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
-       val &= ~BIT(1) | BIT(0);
+       val &= ~(BIT(1) | BIT(0));
        writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
 
        /* Force fanout-27M factor N to 0. */