bnxt_en: Refactor RX/RX AGG ring parameters setup for P5_PLUS

There is some common code for setting up RX and RX AGG ring allocation
parameters for P5_PLUS chips.  Refactor the logic into a new function.

Reviewed-by: Hongguang Gao <hongguang.gao@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Link: https://patch.msgid.link/20250213011240.1640031-7-michael.chan@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 453f5264814527d0cb93c9d51b6e80d9ef0cd430..ac63d3feaa1d2d3b2f2bdef3713a3e9274cb9e8a 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -6944,6 +6944,28 @@ static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
        hwrm_req_drop(bp, req);
 }
 
+static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type,
+                                      struct hwrm_ring_alloc_input *req,
+                                      struct bnxt_ring_struct *ring)
+{
+       struct bnxt_ring_grp_info *grp_info = &bp->grp_info[ring->grp_idx];
+       u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;
+
+       if (ring_type == HWRM_RING_ALLOC_AGG) {
+               req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
+               req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
+               req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
+               enables |= RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID;
+       } else {
+               req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
+               if (NET_IP_ALIGN == 2)
+                       req->flags =
+                               cpu_to_le16(RING_ALLOC_REQ_FLAGS_RX_SOP_PAD);
+       }
+       req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
+       req->enables |= cpu_to_le32(enables);
+}
+
 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
                                    struct bnxt_ring_struct *ring,
                                    u32 ring_type, u32 map_index)
@@ -6995,37 +7017,13 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
                break;
        }
        case HWRM_RING_ALLOC_RX:
-               req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
-               req->length = cpu_to_le32(bp->rx_ring_mask + 1);
-               if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
-                       u16 flags = 0;
-
-                       /* Association of rx ring with stats context */
-                       grp_info = &bp->grp_info[ring->grp_idx];
-                       req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
-                       req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
-                       req->enables |= cpu_to_le32(
-                               RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
-                       if (NET_IP_ALIGN == 2)
-                               flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
-                       req->flags = cpu_to_le16(flags);
-               }
-               break;
        case HWRM_RING_ALLOC_AGG:
-               if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
-                       req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
-                       /* Association of agg ring with rx ring */
-                       grp_info = &bp->grp_info[ring->grp_idx];
-                       req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
-                       req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
-                       req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
-                       req->enables |= cpu_to_le32(
-                               RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
-                               RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
-               } else {
-                       req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
-               }
-               req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
+               req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
+               req->length = (ring_type == HWRM_RING_ALLOC_RX) ?
+                             cpu_to_le32(bp->rx_ring_mask + 1) :
+                             cpu_to_le32(bp->rx_agg_ring_mask + 1);
+               if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
+                       bnxt_set_rx_ring_params_p5(bp, ring_type, req, ring);
                break;
        case HWRM_RING_ALLOC_CMPL:
                req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;