arm: [MVE] Fix predicates for vec_cmp, vec_vcmpu and vcond_mask (PR 115439)

When compiling c-c++-common/vector-compare-3.c with
-march=armv8.1-m.main+mve+fp.dp -mfloat-abi=hard -mfpu=auto
(which enables MVE), we fail to match vcond_mask because operand 3 has
s_register_operand as predicate for a MVE_VPRED mode, but we try to
match:
(insn 26 25 27 2 (set (reg:V4SI 137)
         (unspec:V4SI [
                 (reg:V4SI 144)
                 (reg:V4SI 145)
                 (subreg:V4BI (reg:HI 143) 0)
             ] VPSELQ_S)) "/src/gcc/testsuite/c-c++-common/vector-compare-3.c":23:6 -1
      (nil))

The fix is to use the right predicate: vpr_register_operand.

The patch also fixes vec_cmp and vec_cmpu in the same way.

When testing with
-mthumb/-march=armv8.1-m.main+mve.fp+fp.dp/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto
it fixes the ICES in c-c++-common/vector-compare-3.c,
g++.dg/opt/pr79734.C, g++.dg/tree-ssa/pr111150.C and
gcc.dg/tree-ssa/pr111150.c

	gcc/ChangeLog

	PR target/115439
	* config/arm/mve.md (vec_vcmp, vec_vcmpu, vcond_mask): Use
	vpr_register_operand predicate for MVE_VPRED operands.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0c0337f9ee27a3f8878e870395e56b5fa3fdd3ed..8527bd753e309e1d114dd1de92bfef0a6400aef2 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -4587,7 +4587,7 @@
 ;; Expanders for vec_cmp and vcond
 
 (define_expand "vec_cmp<mode><MVE_vpred>"
-  [(set (match_operand:<MVE_VPRED> 0 "s_register_operand")
+  [(set (match_operand:<MVE_VPRED> 0 "vpr_register_operand")
        (match_operator:<MVE_VPRED> 1 "comparison_operator"
          [(match_operand:MVE_VLD_ST 2 "s_register_operand")
           (match_operand:MVE_VLD_ST 3 "reg_or_zero_operand")]))]
@@ -4600,7 +4600,7 @@
 })
 
 (define_expand "vec_cmpu<mode><MVE_vpred>"
-  [(set (match_operand:<MVE_VPRED> 0 "s_register_operand")
+  [(set (match_operand:<MVE_VPRED> 0 "vpr_register_operand")
        (match_operator:<MVE_VPRED> 1 "comparison_operator"
          [(match_operand:MVE_2 2 "s_register_operand")
           (match_operand:MVE_2 3 "reg_or_zero_operand")]))]
@@ -4614,7 +4614,7 @@
 (define_expand "vcond_mask_<mode><MVE_vpred>"
   [(set (match_operand:MVE_VLD_ST 0 "s_register_operand")
        (if_then_else:MVE_VLD_ST
-         (match_operand:<MVE_VPRED> 3 "s_register_operand")
+         (match_operand:<MVE_VPRED> 3 "vpr_register_operand")
          (match_operand:MVE_VLD_ST 1 "s_register_operand")
          (match_operand:MVE_VLD_ST 2 "s_register_operand")))]
   "TARGET_HAVE_MVE"