clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP

Add required clocks and resets signals for the TSU IP available on the
Renesas RZ/G3E SoC

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index ff015b3b4d2f24ac1715e004be9020441b6206d8..e9cf4342d0cfb3afdabbf426298151ba05c33d50 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -183,6 +183,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(4))),
        DEF_MOD("cru_0_pclk",                   CLK_PLLDTY_DIV16, 13, 4, 6, 20,
                                                BUS_MSTOP(9, BIT(4))),
+       DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
+                                               BUS_MSTOP(2, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -211,6 +213,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
        DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
+       DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {