re PR target/24951 (ICE: RTL check: expected code 'const_int', have 'const_double...

2005-11-21  Paolo Bonzini  <bonzini@gnu.org>

	PR target/24951
	* config/rs6000/rs6000.c (output_vec_const_move): Load cst and
	cst2 only for SPE vectors.

From-SVN: r107312

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fdc3098b922d22c5aad77aabc0cce9fbb01007df..38726f706cf54ea3129ab376ea83bce75a847490 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-11-21  Paolo Bonzini  <bonzini@gnu.org>
+
+       PR target/24951
+       * config/rs6000/rs6000.c (output_vec_const_move): Load cst and
+       cst2 only for SPE vectors.
+
 2005-11-21  David Edelsohn  <edelsohn@gnu.org>
 
        PR target/24953

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fb3c3a1038398ff35600cc5082f4fd9a842d82db..b72c3fdba35fd47c77c12a3a4fe06fe7b2f58194 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2200,9 +2200,6 @@ output_vec_const_move (rtx *operands)
 
   dest = operands[0];
   vec = operands[1];
-
-  cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
-  cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
   mode = GET_MODE (dest);
 
   if (TARGET_ALTIVEC)
@@ -2240,8 +2237,10 @@ output_vec_const_move (rtx *operands)
 
      FIXME: We should probably return # and add post reload
      splitters for these, but this way is so easy ;-).  */
-  operands[1] = GEN_INT (cst);
-  operands[2] = GEN_INT (cst2);
+  cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
+  cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
+  operands[1] = CONST_VECTOR_ELT (vec, 0);
+  operands[2] = CONST_VECTOR_ELT (vec, 1);
   if (cst == cst2)
     return "li %0,%1\n\tevmergelo %0,%0,%0";
   else