platform/x86: mlx-platform: Allow mlxreg-io driver activation for new systems

Allow mlxreg-io platform driver activation for  the next generation
systems, in particular for MQM87xx, MSN34xx, MSN37xx types, which have:
- extended reset causes bits related to ComEx reset, voltage devices
  firmware upgrade, system platform reset;
- additional CPLD device;
- JTAG select capability;

Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>

diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index 750b153aaddc91cf8b20c604d567603ce65c3ce6..af085235f87eabf3d061994d041d681a9871bc6b 100644 (file)
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -1104,6 +1104,118 @@ static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
                .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
 };
 
+/* Platform register access for next generation systems families data */
+static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
+       {
+               .label = "cpld1_version",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld2_version",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld3_version",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_long_pb",
+               .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(0),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_short_pb",
+               .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(1),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_aux_pwr_or_ref",
+               .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(2),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_from_comex",
+               .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(4),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_asic_thermal",
+               .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(7),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_comex_pwr_fail",
+               .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(3),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_voltmon_upgrade_fail",
+               .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(0),
+               .mode = 0444,
+       },
+       {
+               .label = "reset_system",
+               .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(1),
+               .mode = 0444,
+       },
+       {
+               .label = "psu1_on",
+               .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(0),
+               .mode = 0200,
+       },
+       {
+               .label = "psu2_on",
+               .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(1),
+               .mode = 0200,
+       },
+       {
+               .label = "pwr_cycle",
+               .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(2),
+               .mode = 0200,
+       },
+       {
+               .label = "pwr_down",
+               .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(3),
+               .mode = 0200,
+       },
+       {
+               .label = "jtag_enable",
+               .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
+               .mask = GENMASK(7, 0) & ~BIT(4),
+               .mode = 0644,
+       },
+       {
+               .label = "asic_health",
+               .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
+               .mask = MLXPLAT_CPLD_ASIC_MASK,
+               .bit = 1,
+               .mode = 0444,
+       },
+};
+
+static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
+               .data = mlxplat_mlxcpld_default_ng_regs_io_data,
+               .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
+};
+
 /* Platform FAN default */
 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
        {
@@ -1449,6 +1561,7 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
        mlxplat_hotplug->deferred_nr =
                mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
        mlxplat_led = &mlxplat_default_ng_led_data;
+       mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
        mlxplat_fan = &mlxplat_default_fan_data;
 
        return 1;