drm/xe/guc: Introduce enum with offsets for context register H2Gs

Some GuC messages are constructed with incrementing dword counter
rather than referencing specific DWORDs, as described in GuC interface
specification.

This change introduces the definitions of DWORD numbers for parameters
which will need to be referenced in a CTB parser to be added in a
following patch. To ensure correctness of these DWORDs, verification
in form of asserts was added to the message construction code.

v2: Renamed enum members, added ones for single context registration,
  modified asserts to check values rather than indexes.
v3: Reordered assert args to take less lines
v4: Added lengths
v5: Renamed MULTI_LRC_MSG_LEN to MULTI_LRC_MSG_MIN_LEN

Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://lore.kernel.org/r/20250512114018.361843-4-tomasz.lis@intel.com

diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 448afb86e05c7dd45e4923df2ad04ab896afa1f7..ff4f412c28d8cdab7af81a3dba65bd7a1144d816 100644 (file)
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -161,6 +161,37 @@ enum xe_guc_preempt_options {
        XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
 };
 
+enum xe_guc_register_context_param_offsets {
+       XE_GUC_REGISTER_CONTEXT_DATA_0_MBZ = 0,
+       XE_GUC_REGISTER_CONTEXT_DATA_1_FLAGS,
+       XE_GUC_REGISTER_CONTEXT_DATA_2_CONTEXT_INDEX,
+       XE_GUC_REGISTER_CONTEXT_DATA_3_ENGINE_CLASS,
+       XE_GUC_REGISTER_CONTEXT_DATA_4_ENGINE_SUBMIT_MASK,
+       XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER,
+       XE_GUC_REGISTER_CONTEXT_DATA_6_WQ_DESC_ADDR_UPPER,
+       XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER,
+       XE_GUC_REGISTER_CONTEXT_DATA_8_WQ_BUF_BASE_UPPER,
+       XE_GUC_REGISTER_CONTEXT_DATA_9_WQ_BUF_SIZE,
+       XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR,
+       XE_GUC_REGISTER_CONTEXT_MSG_LEN,
+};
+
+enum xe_guc_register_context_multi_lrc_param_offsets {
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_0_MBZ = 0,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_1_FLAGS,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_2_PARENT_CONTEXT,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_3_ENGINE_CLASS,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_4_ENGINE_SUBMIT_MASK,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_6_WQ_DESC_ADDR_UPPER,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_8_WQ_BUF_BASE_UPPER,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_9_WQ_BUF_SIZE,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR,
+       XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_MIN_LEN = 11,
+};
+
 enum xe_guc_report_status {
        XE_GUC_REPORT_STATUS_UNKNOWN = 0x0,
        XE_GUC_REPORT_STATUS_ACKED = 0x1,

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 369be36f7dc5a399d8e67e68e02dac822ff80e65..06e2998b0e2149db848116a4bb1f5b369fd20aa6 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -487,6 +487,15 @@ static void __register_mlrc_exec_queue(struct xe_guc *guc,
                action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));
        }
 
+       /* explicitly checks some fields that we might fixup later */
+       xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER]);
+       xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER]);
+       xe_gt_assert(guc_to_gt(guc), q->width ==
+                    action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS]);
+       xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR]);
        xe_gt_assert(guc_to_gt(guc), len <= MAX_MLRC_REG_SIZE);
 #undef MAX_MLRC_REG_SIZE
 
@@ -511,6 +520,14 @@ static void __register_exec_queue(struct xe_guc *guc,
                info->hwlrca_hi,
        };
 
+       /* explicitly checks some fields that we might fixup later */
+       xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER]);
+       xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER]);
+       xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
+                    action[XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR]);
+
        xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
 }