- env:
- BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
- env:
- - BUILDMAN="t208xrdb t4qds t102*"
+ - BUILDMAN="t208xrdb"
+ - env:
+ - BUILDMAN="t4qds"
+ - env:
+ - BUILDMAN="t102*"
- env:
- BUILDMAN="p1_p2_rdb_pc"
- env:
obj-y += generic.o
obj-y += timer.o
obj-y += devices.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += relocate.o
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += relocate.o
#
# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o timer.o reset.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
#
# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o reset.o timer.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
#endif
#ifdef CONFIG_ARM_ERRATA_454179
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_454179
+ orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_454179:
#endif
#ifdef CONFIG_ARM_ERRATA_430973
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_430973
+ orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x1 << 6) @ Set IBE bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_430973:
#endif
#ifdef CONFIG_ARM_ERRATA_621766
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_621766
+ orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_621766:
#endif
#ifdef CONFIG_ARM_ERRATA_725233
+ mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
+
cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
- bge skip_errata_725233
+ orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
- mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
- orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_l2aux_ctrl
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_725233:
#endif
#ifdef CONFIG_ARM_ERRATA_852421
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
+ stm32f469-disco.dtb
+
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
aliases {
ethernet0 = ð0;
- ethernet1 = ð1;
+ ethernet1 = ð2;
i2c0 = &i2c0;
spi1 = &spi1;
};
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT4>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
+ st,bank-name = "GPIOI";
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
+ st,bank-name = "GPIOJ";
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
+ st,bank-name = "GPIOK";
+ };
+
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_pins_a: usart3@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
+ <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
+ <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_hs_pins_a: usbotg_hs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
+ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+ <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+ <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+ <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+ <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+ <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+ <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+ <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+ <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+ <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+ <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
+ <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
+ <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
+ <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
+ <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
+ slew-rate = <2>;
+ };
+ };
+
+ adc3_in8_pin: adc@200 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+ };
+ };
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
+ <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
+ <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
+ <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
+ };
+ };
+
+ i2c1_pins: i2c1@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+ <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <3>;
+ };
+ };
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
+
+ dcmi_pins: dcmi@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
+ <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
+ <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
+ <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
+ <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
+ <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
+ <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
+ <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
+ <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>,
+ <STM32_PINMUX('C', 9, AF12)>,
+ <STM32_PINMUX('C', 10, AF12)>,
+ <STM32_PINMUX('c', 11, AF12)>,
+ <STM32_PINMUX('C', 12, AF12)>,
+ <STM32_PINMUX('D', 2, AF12)>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>,
+ <STM32_PINMUX('C', 9, AF12)>,
+ <STM32_PINMUX('C', 10, AF12)>,
+ <STM32_PINMUX('C', 11, AF12)>,
+ <STM32_PINMUX('C', 12, AF12)>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Memory configuration from sdram datasheet
+ * IS42S16400J
+ */
+ bank1: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_16
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_3
+ TXSR_7
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2 TRCD_2>;
+ st,sdram-refcount = < 1386 >;
+ };
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ usart1_pins_a: usart1@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D09 */
+ <STM32_PINMUX('E',11, AF12)>, /* D08 */
+ <STM32_PINMUX('E',10, AF12)>, /* D07 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+ <STM32_PINMUX('D',15, AF12)>, /* D01 */
+ <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A09 */
+ <STM32_PINMUX('F',14, AF12)>, /* A08 */
+ <STM32_PINMUX('F',13, AF12)>, /* A07 */
+ <STM32_PINMUX('F',12, AF12)>, /* A06 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+ <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
+ <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
+ slew-rate = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32F429i-DISCO board";
+ compatible = "st,stm32f429i-disco", "st,stm32f429";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x90000000 0x800000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red {
+ gpios = <&gpiog 14 0>;
+ };
+ green {
+ gpios = <&gpiog 13 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpioa 0 0>;
+ };
+ };
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
+};
+
+&clk_hse {
+ clock-frequency = <8000000>;
+};
+
+&crc {
+ status = "okay";
+};
+
+&rtc {
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSI>;
+ status = "okay";
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg_hs {
+ compatible = "st,stm32f4x9-fsotg";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ compatible = "st,stm32f429-pinctrl";
+
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_i2s_ckin: i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ timer2: timer@40000000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000000 0x400>;
+ interrupts = <28>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+ status = "disabled";
+ };
+
+ timers2: timers@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
+ timer3: timer@40000400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000400 0x400>;
+ interrupts = <29>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+ status = "disabled";
+ };
+
+ timers3: timers@40000400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ timer4: timer@40000800 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000800 0x400>;
+ interrupts = <30>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+ status = "disabled";
+ };
+
+ timers4: timers@40000800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+ };
+
+ timers5: timers@40000c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000C00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
+ timer6: timer@40001000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001000 0x400>;
+ interrupts = <54>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+ status = "disabled";
+ };
+
+ timers6: timers@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+ clock-names = "int";
+ status = "disabled";
+
+ timer@5 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timer7: timer@40001400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001400 0x400>;
+ interrupts = <55>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+ status = "disabled";
+ };
+
+ timers7: timers@40001400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+ clock-names = "int";
+ status = "disabled";
+
+ timer@6 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ timers12: timers@40001800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timers@40001c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001C00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ timers14: timers@40002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ rtc: rtc@40002800 {
+ compatible = "st,stm32-rtc";
+ reg = <0x40002800 0x400>;
+ clocks = <&rcc 1 CLK_RTC>;
+ clock-names = "ck_rtc";
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSE>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 1>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
+
+ iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ status = "disabled";
+ };
+
+ usart2: serial@40004400 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
+ status = "disabled";
+ };
+
+ usart3: serial@40004800 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004800 0x400>;
+ interrupts = <39>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
+ status = "disabled";
+ dmas = <&dma1 1 4 0x400 0x0>,
+ <&dma1 3 4 0x400 0x0>;
+ dma-names = "rx", "tx";
+ };
+
+ usart4: serial@40004c00 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <52>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
+ status = "disabled";
+ };
+
+ usart5: serial@40005000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40005000 0x400>;
+ interrupts = <53>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@40005400 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dac: dac@40007400 {
+ compatible = "st,stm32f4-dac-core";
+ reg = <0x40007400 0x400>;
+ resets = <&rcc STM32F4_APB1_RESET(DAC)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ usart7: serial@40007800 {
+ compatible = "st,stm32-uart";
+ reg = <0x40007800 0x400>;
+ interrupts = <82>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
+ status = "disabled";
+ };
+
+ usart8: serial@40007c00 {
+ compatible = "st,stm32-uart";
+ reg = <0x40007c00 0x400>;
+ interrupts = <83>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
+ status = "disabled";
+ };
+
+ timers1: timers@40010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ timers8: timers@40010400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+ };
+
+ usart1: serial@40011000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
+ status = "disabled";
+ dmas = <&dma2 2 4 0x400 0x0>,
+ <&dma2 7 4 0x400 0x0>;
+ dma-names = "rx", "tx";
+ };
+
+ usart6: serial@40011400 {
+ compatible = "st,stm32-uart";
+ reg = <0x40011400 0x400>;
+ interrupts = <71>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
+ status = "disabled";
+ };
+
+ adc: adc@40012000 {
+ compatible = "st,stm32f4-adc-core";
+ reg = <0x40012000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+ clock-names = "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+ interrupt-parent = <&adc>;
+ interrupts = <0>;
+ dmas = <&dma2 0 0 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
+ interrupt-parent = <&adc>;
+ interrupts = <1>;
+ dmas = <&dma2 3 1 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc3: adc@200 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x200>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
+ interrupt-parent = <&adc>;
+ interrupts = <2>;
+ dmas = <&dma2 1 2 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
+ syscfg: system-config@40013800 {
+ compatible = "syscon";
+ reg = <0x40013800 0x400>;
+ };
+
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
+ timers9: timers@40014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@8 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <8>;
+ status = "disabled";
+ };
+ };
+
+ timers10: timers@40014400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ timers11: timers@40014800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ pwrcfg: power-config@40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
+ sdio: sdio@40012c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ interrupts = <49>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
+
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ crc: crc@40023000 {
+ compatible = "st,stm32f4-crc";
+ reg = <0x40023000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+ status = "disabled";
+ };
+
+ rcc: rcc@40023810 {
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
+ assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+ assigned-clock-rates = <1000000>;
+ };
+
+ dma1: dma-controller@40026000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
+ #dma-cells = <4>;
+ };
+
+ dma2: dma-controller@40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
+
+ mac: ethernet@40028000 {
+ compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ interrupts = <61>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
+ <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
+ <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
+ st,syscon = <&syscfg 0x4>;
+ snps,pbl = <8>;
+ snps,mixed-burst;
+ status = "disabled";
+ };
+
+ usbotg_hs: usb@40040000 {
+ compatible = "snps,dwc2";
+ reg = <0x40040000 0x40000>;
+ interrupts = <77>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ usbotg_fs: usb@50000000 {
+ compatible = "st,stm32f4x9-fsotg";
+ reg = <0x50000000 0x40000>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ dcmi: dcmi@50050000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x50050000 0x400>;
+ interrupts = <78>;
+ resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
+ clock-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcmi_pins>;
+ dmas = <&dma2 1 1 0x414 0x3>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ rng: rng@50060800 {
+ compatible = "st,stm32-rng";
+ reg = <0x50060800 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
+
+ };
+ };
+};
+
+&systick {
+ clocks = <&rcc 1 SYSTICK>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+ st,syscfg = <&syscfg>;
+ pinctrl-0 = <&fmc_pins_d32>;
+ pinctrl-names = "default";
+ st,mem_remap = <4>;
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Memory configuration from sdram
+ * MICRON MT48LC4M32B2B5-6A
+ */
+ bank0: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ st,sdram-refcount = < 1292 >;
+ };
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ usart3_pins_a: usart3@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fmc_pins_d32: fmc_d32@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+ <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+ <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+ <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+ <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+ <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+ <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+ <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+ <STM32_PINMUX('H',15, AF12)>, /* D23 */
+ <STM32_PINMUX('H',14, AF12)>, /* D22 */
+ <STM32_PINMUX('H',13, AF12)>, /* D21 */
+ <STM32_PINMUX('H',12, AF12)>, /* D20 */
+ <STM32_PINMUX('H',11, AF12)>, /* D19 */
+ <STM32_PINMUX('H',10, AF12)>, /* D18 */
+ <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+ <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+ <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D09 */
+ <STM32_PINMUX('E',11, AF12)>, /* D08 */
+ <STM32_PINMUX('E',10, AF12)>, /* D07 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+ <STM32_PINMUX('D',15, AF12)>, /* D01 */
+ <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+ <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+ <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A09 */
+ <STM32_PINMUX('F',14, AF12)>, /* A08 */
+ <STM32_PINMUX('F',13, AF12)>, /* A07 */
+ <STM32_PINMUX('F',12, AF12)>, /* A06 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+ <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+ <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+ slew-rate = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f469-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32F469i-DISCO board";
+ compatible = "st,stm32f469i-disco", "st,stm32f469";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x00000000 0x1000000>;
+ };
+
+ aliases {
+ serial0 = &usart3;
+ };
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+ };
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
+};
+
+&rcc {
+ compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
+};
+
+&clk_hse {
+ clock-frequency = <8000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
+&usart3 {
+ pinctrl-0 = <&usart3_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg_fs {
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ compatible = "st,stm32f469-pinctrl";
+
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 6>,
+ <&pinctrl 12 156 4>;
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 3 163 5>;
+ };
+ };
+ };
+};
aliases {
serial0 = &usart1;
spi0 = &qspi;
+ mmc0 = &sdio;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
reg = <0>;
};
};
+
+&sdio {
+ status = "okay";
+ cd-gpios = <&gpioc 13 0>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
u-boot,dm-pre-reloc;
};
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>,
+ <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_b: sdio_pins_b@0 {
+ pins {
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>,
+ <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od_b: sdio_pins_od_b@0 {
+ pins1 {
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+
+ };
+ sdio: sdio@40012c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ interrupts = <49>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
+
+ sdio2: sdio2@40011c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ interrupts = <103>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
};
};
};
aliases {
serial0 = &usart1;
spi0 = &qspi;
+ mmc0 = &sdio2;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
reg = <0>;
};
};
+
+&sdio2 {
+ status = "okay";
+ cd-gpios = <&gpioi 15 0>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
int rockchip_get_clk(struct udevice **devp);
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
#endif
enum stm32_gpio_af af;
};
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+
static inline unsigned stm32_gpio_to_port(unsigned gpio)
{
return gpio / 16;
return gpio % 16;
}
-int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
- const struct stm32_gpio_ctl *gpio_ctl);
-int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
-
#endif /* _STM32_GPIO_H_ */
#define STM32_BUS_MASK 0xFFFF0000
-#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
-
/*
* Register maps
*/
u32 u_id_high;
};
-struct stm32_pwr_regs {
- u32 cr;
- u32 csr;
-};
-
/*
* Registers access macros
*/
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
-#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
-
-/*
- * Peripheral base addresses
- */
-#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
-#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
-#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
-
#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[5 ... 11] = 128 * 1024
};
-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
-
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _MACH_STM32_H_ */
config TARGET_STM32F429_DISCOVERY
bool "STM32F429 Discovery board"
+config TARGET_STM32F469_DISCOVERY
+ bool "STM32F469 Discovery board"
+
source "board/st/stm32f429-discovery/Kconfig"
+source "board/st/stm32f469-discovery/Kconfig"
endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o timer.o
+obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
-
-#define RCC_CR_HSION (1 << 0)
-#define RCC_CR_HSEON (1 << 16)
-#define RCC_CR_HSERDY (1 << 17)
-#define RCC_CR_HSEBYP (1 << 18)
-#define RCC_CR_CSSON (1 << 19)
-#define RCC_CR_PLLON (1 << 24)
-#define RCC_CR_PLLRDY (1 << 25)
-
-#define RCC_PLLCFGR_PLLM_MASK 0x3F
-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK 0x30000
-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
-#define RCC_PLLCFGR_PLLSRC (1 << 22)
-#define RCC_PLLCFGR_PLLN_SHIFT 6
-#define RCC_PLLCFGR_PLLP_SHIFT 16
-#define RCC_PLLCFGR_PLLQ_SHIFT 24
-
-#define RCC_CFGR_AHB_PSC_MASK 0xF0
-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
-#define RCC_CFGR_APB2_PSC_MASK 0xE000
-#define RCC_CFGR_SW0 (1 << 0)
-#define RCC_CFGR_SW1 (1 << 1)
-#define RCC_CFGR_SW_MASK 0x3
-#define RCC_CFGR_SW_HSI 0
-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
-#define RCC_CFGR_SWS0 (1 << 2)
-#define RCC_CFGR_SWS1 (1 << 3)
-#define RCC_CFGR_SWS_MASK 0xC
-#define RCC_CFGR_SWS_HSI 0
-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT 4
-#define RCC_CFGR_PPRE1_SHIFT 10
-#define RCC_CFGR_PPRE2_SHIFT 13
-
-#define RCC_APB1ENR_PWREN (1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
-
-#define PWR_CR_VOS0 (1 << 14)
-#define PWR_CR_VOS1 (1 << 15)
-#define PWR_CR_VOS_MASK 0xC000
-#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#if (CONFIG_SYS_CLK_FREQ == 180000000)
-/* 180 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 360,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#else
-/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 336,
- .pll_p = 2,
- .pll_q = 7,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
- /* Reset RCC configuration */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
- /* Configure for HSE+PLL operation */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
- ;
-
- /* Enable high performance mode, System frequency up to 180 MHz */
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
- writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
- setbits_le32(&STM32_RCC->cfgr, ((
- sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
- | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
- | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
- writel(sys_pll_psc.pll_m
- | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
- | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
- | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
- &STM32_RCC->pllcfgr);
- setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
-
- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
- ;
-
- stm32_flash_latency_cfg(5);
- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
- RCC_CFGR_SWS_PLL)
- ;
-
- return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
- u32 sysclk = 0;
- u32 shift = 0;
- /* Prescaler table lookups for clock computation */
- u8 ahb_psc_table[16] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
- };
- u8 apb_psc_table[8] = {
- 0, 0, 0, 0, 1, 2, 3, 4
- };
-
- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
- RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
- >> RCC_PLLCFGR_PLLN_SHIFT);
- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
- >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
- }
-
- switch (clck) {
- case CLOCK_CORE:
- return sysclk;
- break;
- case CLOCK_AHB:
- shift = ahb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
- >> RCC_CFGR_HPRE_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB1:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
- >> RCC_CFGR_PPRE1_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB2:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
- >> RCC_CFGR_PPRE2_SHIFT)];
- return sysclk >>= shift;
- break;
- default:
- return 0;
- break;
- }
-}
-
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case USART1_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
- break;
- case GPIO_A_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
- break;
- case GPIO_B_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
- break;
- case GPIO_C_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
- break;
- case GPIO_D_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
- break;
- case GPIO_E_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
- break;
- case GPIO_F_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
- break;
- case GPIO_G_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
- break;
- case GPIO_H_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
- break;
- case GPIO_I_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
- break;
- case GPIO_J_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
- break;
- case GPIO_K_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
- break;
- default:
- break;
- }
-}
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
- if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
- writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
- else
- writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
+ writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1,
+ &tim->psc);
writel(0xFFFFFFFF, &tim->arr);
writel(TIM_CR1_CEN, &tim->cr1);
return ret;
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
+ unsigned long max_size;
if (!dram_map[i].size)
break;
dram_map[i].base)
break;
+ /*
+ * Do not use memory that exceeds 32bit address range. U-Boot
+ * relocates itself to the end of the effectively available RAM.
+ * This could be a problem for DMA engines that do not support
+ * 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
+ */
+ if (dram_map[i].base >= 1ULL << 32)
+ break;
+
+ max_size = (1ULL << 32) - dram_map[i].base;
+
+ if (dram_map[i].size > max_size) {
+ gd->ram_size += max_size;
+ break;
+ }
+
gd->ram_size += dram_map[i].size;
}
+ /*
+ * LD20 uses the last 64 byte for each channel for dynamic
+ * DDR PHY training
+ */
+ if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
+ gd->ram_size -= 64;
+
return 0;
}
#
obj-y += interrupts.o
-ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_PCI) += pci_io.o
-endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
#
obj-y += board.o
-ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
obj-$(CONFIG_DM_VIDEO) += video_display.o
-endif
#
obj-y += arndale_spl.o
-
-ifndef CONFIG_SPL_BUILD
obj-y += arndale.o
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
obj-y += espresso7420.o
-endif
Please use the correct device node for your setup instead
of "/dev/sdX" here!
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI: 00010
+ - SD/eMMC: 00111
+ - M.2 SSD: 11100
+ - UART: 01001 [1]
+
+[1]: According to SolidRun's manual, 11110 should be used for UART booting on
+ the ClearFog 'Pro' variant.
+ However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
+ mentionend for the 'Base' variant does).
+
Boot from UART:
---------------
Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
to your host.
-Set the SW1 DIP switches to UART boot (0: OFF, 1: ON):
-
- ClearFog Base: 01001
- ClearFog Pro: 11110
+Set the SW1 DIP switches to UART boot (see above).
Run the following command to initiate U-Boot download:
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
-obj-y := spear600.o
-endif
+obj-y += spear600.o
#include <common.h>
#include <dm.h>
-#include <stm32_rcc.h>
+
#include <asm/io.h>
-#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
-#include <dm/platform_data/serial_stm32.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>
DECLARE_GLOBAL_DATA_PTR;
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
- .mode = STM32_GPIO_MODE_OUT,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_UP,
- .af = STM32_GPIO_USART
-};
-
-static const struct stm32_gpio_dsc usart_gpio[] = {
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
-};
-
-int uart_setup_gpio(void)
-{
- int i;
- int rv = 0;
-
- clock_setup(GPIO_A_CLOCK_CFG);
- for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
- rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
-const struct stm32_gpio_ctl gpio_ctl_fmc = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF12
-};
-
-static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
- /* Chip is LQFP144, see DM00077036.pdf for details */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
-};
-
-static int fmc_setup_gpio(void)
-{
- int rv = 0;
- int i;
-
- clock_setup(GPIO_B_CLOCK_CFG);
- clock_setup(GPIO_C_CLOCK_CFG);
- clock_setup(GPIO_D_CLOCK_CFG);
- clock_setup(GPIO_E_CLOCK_CFG);
- clock_setup(GPIO_F_CLOCK_CFG);
- clock_setup(GPIO_G_CLOCK_CFG);
-
- for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
- rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
- &gpio_ctl_fmc);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
-/*
- * STM32 RCC FMC specific definitions
- */
-#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
-
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
- u32 tmp = freq/1000000;
- return (tmp * ns) / 1000;
-}
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS 3 /* 3 cycles */
-#define SDRAM_NB 1 /* Number of banks */
-#define SDRAM_MWID 1 /* 16 bit memory */
-
-#define SDRAM_NR 0x1 /* 12-bit row */
-#define SDRAM_NC 0x0 /* 8-bit col */
-#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
-#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD (NS2CLK(14) - 1)
-#define SDRAM_TRCD (NS2CLK(15) - 1)
-#define SDRAM_TRP (NS2CLK(15) - 1)
-#define SDRAM_TRAS (NS2CLK(42) - 1)
-#define SDRAM_TRC (NS2CLK(63) - 1)
-#define SDRAM_TRFC (NS2CLK(63) - 1)
-#define SDRAM_TCDL (1 - 1)
-#define SDRAM_TRDL (2 - 1)
-#define SDRAM_TBDL (1 - 1)
-#define SDRAM_TREF 1386
-#define SDRAM_TCCD (1 - 1)
-
-#define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */
-#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
-
-/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
-#define SDRAM_TWR max(\
- (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
- (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
-)
-
-#define SDRAM_MODE_BL_SHIFT 0
-#define SDRAM_MODE_CAS_SHIFT 4
-#define SDRAM_MODE_BL 0
-#define SDRAM_MODE_CAS SDRAM_CAS
-
int dram_init(void)
{
- u32 freq;
int rv;
+ struct udevice *dev;
- rv = fmc_setup_gpio();
- if (rv)
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
return rv;
+ }
- setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
-
- /*
- * Get frequency for NS2CLK calculation.
- */
- freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
- writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
- | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
- | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr1);
-
- writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
- | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
- | SDRAM_NB << FMC_SDCR_NB_SHIFT
- | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
- | SDRAM_NR << FMC_SDCR_NR_SHIFT
- | SDRAM_NC << FMC_SDCR_NC_SHIFT
- | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
- | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr2);
-
- writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
- | SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
- &STM32_SDRAM_FMC->sdtr1);
-
- writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
- | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
- | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
- | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
- | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
- | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
- | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
- &STM32_SDRAM_FMC->sdtr2);
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(200); /* 200 us delay, page 10, "Power-Up" */
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
- | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
- | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
- << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
-
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
- &STM32_SDRAM_FMC->sdcmr);
-
- FMC_BUSY_WAIT();
-
- /* Refresh timer */
- writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
-
- /*
- * Fill in global info with description of SRAM configuration
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
-
- gd->ram_size = CONFIG_SYS_RAM_SIZE;
+ if (fdtdec_setup_memory_size() != 0)
+ rv = -EINVAL;
return rv;
}
-static const struct stm32_serial_platdata serial_platdata = {
- .base = (struct stm32_usart *)STM32_USART1_BASE,
-};
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
-U_BOOT_DEVICE(stm32_serials) = {
- .name = "serial_stm32",
- .platdata = &serial_platdata,
-};
+ return 0;
+}
u32 get_board_rev(void)
{
int board_early_init_f(void)
{
- int res;
-
- configure_clocks();
-
- res = uart_setup_gpio();
- if (res)
- return res;
- clock_setup(USART1_CLOCK_CFG);
-
return 0;
}
--- /dev/null
+if TARGET_STM32F469_DISCOVERY
+
+config SYS_BOARD
+ string
+ default "stm32f469-discovery"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stm32f4"
+
+config SYS_CONFIG_NAME
+ string
+ default "stm32f469-discovery"
+
+endif
--- /dev/null
+STM32F469-DISCOVERY BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: board/st/stm32f469-discovery/
+F: include/configs/stm32f469-discovery.h
+F: configs/stm32f469-discovery_defconfig
--- /dev/null
+#
+# Copyright (C) STMicroelectronics SA 2017
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := stm32f469-discovery.o
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+ if (fdtdec_setup_memory_size() != 0)
+ rv = -EINVAL;
+
+ return rv;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char serialno[25];
+ u32 u_id_low, u_id_mid, u_id_high;
+
+ if (!env_get("serial#")) {
+ u_id_low = readl(&STM32_U_ID->u_id_low);
+ u_id_mid = readl(&STM32_U_ID->u_id_mid);
+ u_id_high = readl(&STM32_U_ID->u_id_high);
+ sprintf(serialno, "%08x%08x%08x",
+ u_id_high, u_id_mid, u_id_low);
+ env_set("serial#", serialno);
+ }
+
+ return 0;
+}
+#endif
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_ARM=y
CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIMER=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_LIBFDT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
+CONFIG_STM32X7_SERIAL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_STM32F4=y
+CONFIG_TARGET_STM32F469_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+# CONFIG_BLK is not set
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
+CONFIG_DM_MMC=y
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
+CONFIG_STM32X7_SERIAL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_DM_GPIO=y
CONFIG_MISC=y
CONFIG_STM32_RCC=y
-# CONFIG_MMC is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_NAND=y
CONFIG_NAND_DENALI_DT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
#include <asm/io.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
+enum periph_clock {
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ STMMAC_CLOCK_CFG,
+};
+
struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 12);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3328_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 12);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return ret;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3368_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 15);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return ret;
}
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3399_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 21);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
return 0;
}
+static int rk3399_pmuclk_bind(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ int ret;
+
+ ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 2);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+ return 0;
+}
+
static const struct udevice_id rk3399_pmuclk_ids[] = {
{ .compatible = "rockchip,rk3399-pmucru" },
{ }
.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
.ops = &rk3399_pmuclk_ops,
.probe = rk3399_pmuclk_probe,
+ .bind = rk3399_pmuclk_bind,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
.platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
#endif
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3368_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 13);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
-obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const unsigned long io_base[] = {
- STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
- STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
- STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
-#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
- x->pupd > 2 || x->speed > 3)
-
-int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
- const struct stm32_gpio_ctl *ctl)
-{
- struct stm32_gpio_regs *gpio_regs;
- u32 i;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
- if (CHECK_CTL(ctl)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- i = (dsc->pin & 0x07) * 4;
- clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
-
- i = dsc->pin * 2;
-
- clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
- clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
- clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
- clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- if (state)
- writel(1 << dsc->pin, &gpio_regs->bsrr);
- else
- writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
-out:
- return rv;
-}
-
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_IN;
- ctl.otype = STM32_GPIO_OTYPE_PP;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- return stm32_gpio_config(&dsc, &ctl);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
- int res;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_OUT;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- res = stm32_gpio_config(&dsc, &ctl);
- if (res < 0)
- goto out;
- res = stm32_gpout_set(&dsc, value);
-out:
- return res;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpin_get(&dsc);
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpout_set(&dsc, value);
-}
This MAC is present in Andestech SoCs.
config MVNETA
- bool "Marvell Armada 385 network interface support"
- depends on ARMADA_XP || ARMADA_38X
+ bool "Marvell Armada XP/385/3700 network interface support"
+ depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
select PHYLIB
help
This driver supports the network interface units in the
- Marvell ARMADA XP and 38X SoCs
+ Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
-obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+++ /dev/null
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Alex Bounine <alexandreb@tundra.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI initialisation for the Tsi108 EMU board.
- */
-
-#include <config.h>
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <tsi108.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-struct pci_controller local_hose;
-
-void tsi108_clear_pci_error (void)
-{
- u32 err_stat, err_addr, pci_stat;
-
- /*
- * Quietly clear errors signalled as result of PCI/X configuration read
- * requests.
- */
- /* Read PB Error Log Registers */
- err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS);
- err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_AERR);
- if (err_stat & PB_ERRCS_ES) {
- /* Clear PCI/X bus errors if applicable */
- if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
- /* Clear error flag */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS) =
- PB_ERRCS_ES;
-
- /* Clear read error reported in PB_ISR */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ISR) =
- PB_ISR_PBS_RD_ERR;
-
- /* Clear errors reported by PCI CSR (Normally Master Abort) */
- pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_CSR);
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_CSR) =
- pci_stat;
-
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
- }
- }
-
- return;
-}
-
-unsigned int __get_pci_config_dword (u32 addr)
-{
- unsigned int retval;
-
- __asm__ __volatile__ (" lwbrx %0,0,%1\n"
- "1: eieio\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: li %0,-1\n"
- " b 2b\n"
- ".section __ex_table,\"a\"\n"
- " .align 2\n"
- " .long 1b,3b\n"
- ".section .text.__get_pci_config_dword"
- : "=r"(retval) : "r"(addr));
-
- return (retval);
-}
-
-static int tsi108_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
- *value = __get_pci_config_dword(dev);
- if (0xFFFFFFFF == *value)
- tsi108_clear_pci_error ();
- return 0;
-}
-
-static int tsi108_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
-
- out_le32 ((volatile unsigned *)dev, value);
-
- return 0;
-}
-
-void pci_init_board (void)
-{
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region (hose->regions + 1,
- CONFIG_SYS_PCI_MEM_BUS,
- CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (hose->regions + 2,
- CONFIG_SYS_PCI_IO_BUS,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops (hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- tsi108_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- tsi108_write_config_dword);
-
- pci_register_hose (hose);
-
- hose->last_busno = pci_hose_scan (hose);
-
- debug ("Done PCI initialization\n");
- return;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(local_hose.first_busno);
- tmp[1] = cpu_to_be32(local_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
if ARCH_MVEBU
config PINCTRL_ARMADA_37XX
- depends on ARMADA_3700
+ depends on ARMADA_3700 && PINCTRL_FULL
bool "Armada 37xx pin control driver"
help
Support pin multiplexing and pin configuration control on
Marvell's Armada-37xx SoC.
config PINCTRL_ARMADA_8K
- depends on ARMADA_8K
+ depends on ARMADA_8K && PINCTRL_FULL
bool "Armada 7k/8k pin control driver"
help
Support pin multiplexing and pin configuration control on
};
static const struct udevice_id stm32_pinctrl_ids[] = {
+ { .compatible = "st,stm32f429-pinctrl" },
+ { .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ }
#include <ram.h>
#include <asm/io.h>
+#define MEM_MODE_MASK GENMASK(2, 0)
+#define NOT_FOUND 0xff
+
DECLARE_GLOBAL_DATA_PTR;
struct stm32_fmc_regs {
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
+ struct ofnode_phandle_args args;
+ u32 *syscfg_base;
+ u32 mem_remap;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
+ int ret;
+
+ mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+ if (mem_remap != NOT_FOUND) {
+ ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (ret) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ ret);
+ return ret;
+ }
+
+ syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+ /* set memory mapping selection */
+ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+ } else {
+ debug("%s: cannot find st,mem_remap property\n", __func__);
+ }
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
resets that are supported by watchdog. The main limitation though
is that some reset signals, like I2C or MISC reset multiple devices.
+config RESET_ROCKCHIP
+ bool "Reset controller driver for Rockchip SoCs"
+ depends on DM_RESET && ARCH_ROCKCHIP && CLK
+ default y
+ help
+ Support for reset controller on rockchip SoC. The main limitation
+ though is that some reset signals, like I2C or MISC reset multiple
+ devices.
+
endmenu
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <linux/io.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+/*
+ * Each reg has 16 bits reset signal for devices
+ * Note: Not including rk2818 and older SoCs
+ */
+#define ROCKCHIP_RESET_NUM_IN_REG 16
+
+struct rockchip_reset_priv {
+ void __iomem *base;
+ /* Rockchip reset reg locate at cru controller */
+ u32 reset_reg_offset;
+ /* Rockchip reset reg number */
+ u32 reset_reg_num;
+};
+
+static int rockchip_reset_request(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
+
+ if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rockchip_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+ int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id,
+ priv->base + (bank * 4));
+
+ rk_setreg(priv->base + (bank * 4), BIT(offset));
+
+ return 0;
+}
+
+static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+ int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id,
+ priv->base + (bank * 4));
+
+ rk_clrreg(priv->base + (bank * 4), BIT(offset));
+
+ return 0;
+}
+
+struct reset_ops rockchip_reset_ops = {
+ .request = rockchip_reset_request,
+ .free = rockchip_reset_free,
+ .rst_assert = rockchip_reset_assert,
+ .rst_deassert = rockchip_reset_deassert,
+};
+
+static int rockchip_reset_probe(struct udevice *dev)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = dev_read_addr_size(dev, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
+ return -EINVAL;
+
+ addr += priv->reset_reg_offset;
+ priv->base = ioremap(addr, size);
+
+ debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
+ priv->base, priv->reset_reg_offset, priv->reset_reg_num);
+
+ return 0;
+}
+
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ struct udevice *rst_dev;
+ struct rockchip_reset_priv *priv;
+ int ret;
+
+ ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
+ dev_ofnode(pdev), &rst_dev);
+ if (ret) {
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+ return ret;
+ }
+ priv = malloc(sizeof(struct rockchip_reset_priv));
+ priv->reset_reg_offset = reg_offset;
+ priv->reset_reg_num = reg_number;
+ rst_dev->priv = priv;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_reset) = {
+ .name = "rockchip_reset",
+ .id = UCLASS_RESET,
+ .probe = rockchip_reset_probe,
+ .ops = &rockchip_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
+};
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32.h>
-
-struct stm32_usart {
- u32 sr;
- u32 dr;
- u32 brr;
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 gtpr;
-};
-
-#define USART_CR1_RE (1 << 2)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_UE (1 << 13)
-
-#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE (1 << 7)
-
-#define USART_BRR_F_MASK 0xF
-#define USART_BRR_M_SHIFT 4
-#define USART_BRR_M_MASK 0xFFF0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
-{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- u32 clock, int_div, frac_div, tmp;
-
- if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
- clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
- clock = clock_get(CLOCK_APB2);
- else
- return -EINVAL;
-
- int_div = (25 * clock) / (4 * baudrate);
- tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
- frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
- tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
- writel(tmp, &usart->brr);
-
- return 0;
-}
-
-static int stm32_serial_getc(struct udevice *dev)
-{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
-
- if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
- return -EAGAIN;
-
- return readl(&usart->dr);
-}
-
-static int stm32_serial_putc(struct udevice *dev, const char c)
-{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
-
- if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
- return -EAGAIN;
-
- writel(c, &usart->dr);
-
- return 0;
-}
-
-static int stm32_serial_pending(struct udevice *dev, bool input)
-{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
-
- if (input)
- return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
- else
- return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
-}
-
-static int stm32_serial_probe(struct udevice *dev)
-{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
-
- return 0;
-}
-
-static const struct dm_serial_ops stm32_serial_ops = {
- .putc = stm32_serial_putc,
- .pending = stm32_serial_pending,
- .getc = stm32_serial_getc,
- .setbrg = stm32_serial_setbrg,
-};
-
-U_BOOT_DRIVER(serial_stm32) = {
- .name = "serial_stm32",
- .id = UCLASS_SERIAL,
- .ops = &stm32_serial_ops,
- .probe = stm32_serial_probe,
- .flags = DM_FLAG_PRE_RELOC,
-};
get_name(dentptr, s_name);
- if (strcmp(filename, s_name)
- && strcmp(filename, l_name)) {
+ if (strncasecmp(filename, s_name, sizeof(s_name)) &&
+ strncasecmp(filename, l_name, sizeof(l_name))) {
debug("Mismatch: |%s|%s|\n",
s_name, l_name);
dentptr++;
#define __MIGO_R_H
#define CONFIG_CPU_SH7722 1
-#define CONFIG_MIGO_R 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define __AP325RXA_H
#define CONFIG_CPU_SH7723 1
-#define CONFIG_AP325RXA 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define __AP_SH4A_4A_H
#define CONFIG_CPU_SH7734 1
-#define CONFIG_AP_SH4A_4A 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_ASPENITE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_CALIMAIN
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_DOCKSTAR /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
*/
#define CONFIG_CPU_SH7724 1
-#define CONFIG_ECOVEC 1
#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_MARVELL 1
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_88F5182 1 /* SOC Name */
-#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
#include <asm/arch/orion5x.h>
/*
#define __ESPT_H
#define CONFIG_CPU_SH7763 1
-#define CONFIG_ESPT 1
#define __LITTLE_ENDIAN 1
#define CONFIG_ENV_OVERWRITE 1
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_GOFLEXHOME /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_MACH_GURUPLUG /* Machine type */
/*
* Standard filesystems
#define CONFIG_MARVELL
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
/* CPU and platform */
#define CONFIG_CPU_SH7720 1
-#define CONFIG_MPR2 1
#define CONFIG_DISPLAY_BOARDINFO
#define __MS7720SE_H
#define CONFIG_CPU_SH7720 1
-#define CONFIG_MS7720SE 1
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_LOADADDR 0x8E000000
#define __MS7722SE_H
#define CONFIG_CPU_SH7722 1
-#define CONFIG_MS7722SE 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CPU_SH7750 1
/* #define CONFIG_CPU_SH7751 1 */
/* #define CONFIG_CPU_TYPE_R 1 */
-#define CONFIG_MS7750SE 1
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SUPPORT_VFAT
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x4d00000\0" \
+ "pxefile_addr_r=0x4e00000\0" \
+ "fdt_addr_r=0x4f00000\0" \
+ "kernel_addr_r=0x5000000\0" \
+ "ramdisk_addr_r=0x8000000\0" \
+ BOOTENV
+
#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_OPENRD_BASE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
#define __R0P7734_H
#define CONFIG_CPU_SH7734 1
-#define CONFIG_R0P7734 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define __CONFIG_H
#define CONFIG_CPU_SH7751 1
-#define CONFIG_CPU_SH_TYPE_R 1
-#define CONFIG_R2DPLUS 1
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
#define __RSK7203_H
#define CONFIG_CPU_SH7203 1
-#define CONFIG_RSK7203 1
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
#define __RSK7264_H
#define CONFIG_CPU_SH7264 1
-#define CONFIG_RSK7264 1
#define CONFIG_DISPLAY_BOARDINFO
#define __RSK7269_H
#define CONFIG_CPU_SH7269 1
-#define CONFIG_RSK7269 1
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
-#define CONFIG_MACH_GONI 1 /* working with Goni */
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#define __SH7752EVB_H
#define CONFIG_CPU_SH7752 1
-#define CONFIG_SH7752EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define __SH7753EVB_H
#define CONFIG_CPU_SH7753 1
-#define CONFIG_SH7753EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define __SH7757LCR_H
#define CONFIG_CPU_SH7757 1
-#define CONFIG_SH7757LCR 1
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
#define __SH7763RDP_H
#define CONFIG_CPU_SH7763 1
-#define CONFIG_SH7763RDP 1
#define __LITTLE_ENDIAN 1
#define CONFIG_ENV_OVERWRITE 1
#define __SH7785LCR_H
#define CONFIG_CPU_SH7785 1
-#define CONFIG_SH7785LCR 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevice=0:1\0" \
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
/*
* Commands configuration
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_RAM_SIZE (8 << 20)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xD0000000
#define CONFIG_RED_LED 110
#define CONFIG_GREEN_LED 109
-#define CONFIG_STM32_GPIO
#define CONFIG_STM32_FLASH
-#define CONFIG_STM32_SERIAL
#define CONFIG_STM32_HSE_HZ 8000000
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_STM32F4DISCOVERY
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_RAM_FREQ_DIV 2
+#define CONFIG_SYS_RAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0x00400000
+#define CONFIG_LOADADDR 0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT 12
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (128 << 10)
+#define CONFIG_ENV_SIZE (8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_STM32_HSE_HZ 8000000
+#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+#define CONFIG_BOOTCOMMAND \
+ "run boot_sd"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 3
-/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
-#define CONFIG_SYS_MEM_TOP_HIDE 64
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
/* Timing = value +1 cycles */
#define TMRD_1 (1 - 1)
#define TMRD_2 (2 - 1)
+#define TMRD_3 (3 - 1)
#define TXSR_1 (1 - 1)
#define TXSR_6 (6 - 1)
+#define TXSR_7 (7 - 1)
#define TRAS_1 (1 - 1)
#define TRAS_4 (4 - 1)
#define TRC_6 (6 - 1)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the STM32F4 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
+#define _DT_BINDINGS_MFD_STM32F4_RCC_H
+
+/* AHB1 */
+#define STM32F4_RCC_AHB1_GPIOA 0
+#define STM32F4_RCC_AHB1_GPIOB 1
+#define STM32F4_RCC_AHB1_GPIOC 2
+#define STM32F4_RCC_AHB1_GPIOD 3
+#define STM32F4_RCC_AHB1_GPIOE 4
+#define STM32F4_RCC_AHB1_GPIOF 5
+#define STM32F4_RCC_AHB1_GPIOG 6
+#define STM32F4_RCC_AHB1_GPIOH 7
+#define STM32F4_RCC_AHB1_GPIOI 8
+#define STM32F4_RCC_AHB1_GPIOJ 9
+#define STM32F4_RCC_AHB1_GPIOK 10
+#define STM32F4_RCC_AHB1_CRC 12
+#define STM32F4_RCC_AHB1_BKPSRAM 18
+#define STM32F4_RCC_AHB1_CCMDATARAM 20
+#define STM32F4_RCC_AHB1_DMA1 21
+#define STM32F4_RCC_AHB1_DMA2 22
+#define STM32F4_RCC_AHB1_DMA2D 23
+#define STM32F4_RCC_AHB1_ETHMAC 25
+#define STM32F4_RCC_AHB1_ETHMACTX 26
+#define STM32F4_RCC_AHB1_ETHMACRX 27
+#define STM32F4_RCC_AHB1_ETHMACPTP 28
+#define STM32F4_RCC_AHB1_OTGHS 29
+#define STM32F4_RCC_AHB1_OTGHSULPI 30
+
+#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
+
+/* AHB2 */
+#define STM32F4_RCC_AHB2_DCMI 0
+#define STM32F4_RCC_AHB2_CRYP 4
+#define STM32F4_RCC_AHB2_HASH 5
+#define STM32F4_RCC_AHB2_RNG 6
+#define STM32F4_RCC_AHB2_OTGFS 7
+
+#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F4_RCC_AHB3_FMC 0
+#define STM32F4_RCC_AHB3_QSPI 1
+
+#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F4_RCC_APB1_TIM2 0
+#define STM32F4_RCC_APB1_TIM3 1
+#define STM32F4_RCC_APB1_TIM4 2
+#define STM32F4_RCC_APB1_TIM5 3
+#define STM32F4_RCC_APB1_TIM6 4
+#define STM32F4_RCC_APB1_TIM7 5
+#define STM32F4_RCC_APB1_TIM12 6
+#define STM32F4_RCC_APB1_TIM13 7
+#define STM32F4_RCC_APB1_TIM14 8
+#define STM32F4_RCC_APB1_WWDG 11
+#define STM32F4_RCC_APB1_SPI2 14
+#define STM32F4_RCC_APB1_SPI3 15
+#define STM32F4_RCC_APB1_UART2 17
+#define STM32F4_RCC_APB1_UART3 18
+#define STM32F4_RCC_APB1_UART4 19
+#define STM32F4_RCC_APB1_UART5 20
+#define STM32F4_RCC_APB1_I2C1 21
+#define STM32F4_RCC_APB1_I2C2 22
+#define STM32F4_RCC_APB1_I2C3 23
+#define STM32F4_RCC_APB1_CAN1 25
+#define STM32F4_RCC_APB1_CAN2 26
+#define STM32F4_RCC_APB1_PWR 28
+#define STM32F4_RCC_APB1_DAC 29
+#define STM32F4_RCC_APB1_UART7 30
+#define STM32F4_RCC_APB1_UART8 31
+
+#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F4_RCC_APB2_TIM1 0
+#define STM32F4_RCC_APB2_TIM8 1
+#define STM32F4_RCC_APB2_USART1 4
+#define STM32F4_RCC_APB2_USART6 5
+#define STM32F4_RCC_APB2_ADC1 8
+#define STM32F4_RCC_APB2_ADC2 9
+#define STM32F4_RCC_APB2_ADC3 10
+#define STM32F4_RCC_APB2_SDIO 11
+#define STM32F4_RCC_APB2_SPI1 12
+#define STM32F4_RCC_APB2_SPI4 13
+#define STM32F4_RCC_APB2_SYSCFG 14
+#define STM32F4_RCC_APB2_TIM9 16
+#define STM32F4_RCC_APB2_TIM10 17
+#define STM32F4_RCC_APB2_TIM11 18
+#define STM32F4_RCC_APB2_SPI5 20
+#define STM32F4_RCC_APB2_SPI6 21
+#define STM32F4_RCC_APB2_SAI1 22
+#define STM32F4_RCC_APB2_LTDC 26
+#define STM32F4_RCC_APB2_DSI 27
+
+#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
--- /dev/null
+#ifndef _DT_BINDINGS_STM32_PINFUNC_H
+#define _DT_BINDINGS_STM32_PINFUNC_H
+
+/* define PIN modes */
+#define GPIO 0x0
+#define AF0 0x1
+#define AF1 0x2
+#define AF2 0x3
+#define AF3 0x4
+#define AF4 0x5
+#define AF5 0x6
+#define AF6 0x7
+#define AF7 0x8
+#define AF8 0x9
+#define AF9 0xa
+#define AF10 0xb
+#define AF11 0xc
+#define AF12 0xd
+#define AF13 0xe
+#define AF14 0xf
+#define AF15 0x10
+#define ANALOG 0x11
+
+/* define Pins number*/
+#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
+
+#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+
+#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
+
#define STM32F746_PA15_FUNC_EVENTOUT 0xf10
#define STM32F746_PA15_FUNC_ANALOG 0xf11
-
#define STM32F746_PB0_FUNC_GPIO 0x1000
#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+
+#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b
+
#define STM32F746_PB3_FUNC_EVENTOUT 0x1310
#define STM32F746_PB3_FUNC_ANALOG 0x1311
#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+
+#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b
+
#define STM32F746_PB4_FUNC_EVENTOUT 0x1410
#define STM32F746_PB4_FUNC_ANALOG 0x1411
#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
#define STM32F746_PD6_FUNC_USART2_RX 0x3608
+
+#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c
+
#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
#define STM32F746_PD6_FUNC_DCMI_D10 0x360e
#define STM32F746_PD6_FUNC_LCD_B2 0x360f
#define STM32F746_PD7_FUNC_GPIO 0x3700
#define STM32F746_PD7_FUNC_USART2_CK 0x3708
#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
+
+#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c
+
#define STM32F746_PD7_FUNC_FMC_NE1 0x370d
#define STM32F746_PD7_FUNC_EVENTOUT 0x3710
#define STM32F746_PD7_FUNC_ANALOG 0x3711
#define STM32F746_PG9_FUNC_USART6_RX 0x6909
#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
+
+#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c
+
#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
#define STM32F746_PG9_FUNC_EVENTOUT 0x6910
#define STM32F746_PG10_FUNC_GPIO 0x6a00
#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
+
+#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c
+
#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define ALIGN_DOWN(x, a) ALIGN((x) - ((a) - 1), (a))
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
CONFIG_AMCORE
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
-CONFIG_AP325RXA
CONFIG_APBH_DMA
CONFIG_APBH_DMA_BURST
CONFIG_APBH_DMA_BURST8
CONFIG_APER_1_BASE
CONFIG_APER_SIZE
CONFIG_APUS_FAST_EXCEPT
-CONFIG_AP_SH4A_4A
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_CPU_INIT
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_CPU_SH7763
CONFIG_CPU_SH7780
CONFIG_CPU_SH7785
-CONFIG_CPU_SH_TYPE_R
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CQSPI_DECODER
CONFIG_ECC_SRAM_ADDR_MASK
CONFIG_ECC_SRAM_ADDR_SHIFT
CONFIG_ECC_SRAM_REQ_BIT
-CONFIG_ECOVEC
CONFIG_ECOVEC_ROMIMAGE_ADDR
CONFIG_EDB9301
CONFIG_EDB9302
CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
CONFIG_ESDHC_HC_BLK_ADDR
CONFIG_ESPRESSO7420
-CONFIG_ESPT
CONFIG_ET1100_BASE
CONFIG_ETH1ADDR
CONFIG_ETH2ADDR
CONFIG_MACB2_PHY
CONFIG_MACB3_PHY
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_ASPENITE
-CONFIG_MACH_DAVINCI_CALIMAIN
CONFIG_MACH_DAVINCI_DA850_EVM
-CONFIG_MACH_DOCKSTAR
-CONFIG_MACH_EDMINIV2
-CONFIG_MACH_GOFLEXHOME
-CONFIG_MACH_GONI
-CONFIG_MACH_GURUPLUG
-CONFIG_MACH_KM_KIRKWOOD
CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_OPENRD_BASE
-CONFIG_MACH_SHEEVAPLUG
CONFIG_MACH_SPECIFIC
CONFIG_MACH_TYPE
CONFIG_MACH_TYPE_COMPAT_REV
CONFIG_MENUPROMPT
CONFIG_MENU_SHOW
CONFIG_MFG_ENV_SETTINGS
-CONFIG_MIGO_R
CONFIG_MII
CONFIG_MIIM_ADDRESS
CONFIG_MII_DEFAULT_TSEC
CONFIG_MPC8XXX_SPI
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MPLL_FREQ
-CONFIG_MPR2
CONFIG_MP_CLK_FREQ
-CONFIG_MS7720SE
-CONFIG_MS7722SE
-CONFIG_MS7750SE
CONFIG_MSHC_FREQ
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_QSPI_QUAD_SUPPORT
CONFIG_QSPI_SEL_GPIO
CONFIG_QUOTA
-CONFIG_R0P7734
-CONFIG_R2DPLUS
CONFIG_R7780MP
CONFIG_R8A66597_BASE_ADDR
CONFIG_R8A66597_ENDIAN
CONFIG_ROM_STUBS
CONFIG_ROOTFS_OFFSET
CONFIG_ROOTPATH
-CONFIG_RSK7203
-CONFIG_RSK7264
-CONFIG_RSK7269
CONFIG_RTC_DS1337
CONFIG_RTC_DS1337_NOOSC
CONFIG_RTC_DS1338
CONFIG_SH4_PCI
CONFIG_SH73A0
CONFIG_SH7751_PCI
-CONFIG_SH7752EVB
-CONFIG_SH7753EVB
-CONFIG_SH7757LCR
CONFIG_SH7757LCR_DDR_ECC
-CONFIG_SH7763RDP
CONFIG_SH7780_PCI
CONFIG_SH7780_PCI_BAR
CONFIG_SH7780_PCI_LAR
CONFIG_SH7780_PCI_LSR
-CONFIG_SH7785LCR
CONFIG_SHARP_LM8V31
CONFIG_SHARP_LQ035Q7DH06
CONFIG_SHEEVA_88SV131
--- /dev/null
+#!/bin/bash
+#
+######################################################
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0
+# https://spdx.org/licenses
+#
+# Author: Konstantin Porotchkin kostap@marvell.com
+#
+# Version 0.3
+#
+# UART recovery downloader for Armada SoCs
+#
+######################################################
+
+port=$1
+file=$2
+speed=$3
+
+pattern_repeat=1500
+default_baudrate=115200
+tmpfile=/tmp/xmodem.pattern
+tools=( dd stty sx minicom )
+
+case "$3" in
+ 2)
+ fast_baudrate=230400
+ prefix="\xF2"
+ ;;
+ 4)
+ fast_baudrate=460800
+ prefix="\xF4"
+ ;;
+ 8)
+ fast_baudrate=921600
+ prefix="\xF8"
+ ;;
+ *)
+ fast_baudrate=$default_baudrate
+ prefix="\xBB"
+esac
+
+if [[ -z "$port" || -z "$file" ]]
+then
+ echo -e "\nMarvell recovery image downloader for Armada SoC family."
+ echo -e "Command syntax:"
+ echo -e "\t$(basename $0) <port> <file> [2|4|8]"
+ echo -e "\tport - serial port the target board connected to"
+ echo -e "\tfile - recovery boot image for target download"
+ echo -e "\t2|4|8 - times to increase the default serial port speed by"
+ echo -e "For example - load the image over ttyUSB0 @ 460800 baud:"
+ echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n"
+ echo -e "=====WARNING====="
+ echo -e "- The speed-up option is not awailable in SoC families prior to A8K+"
+ echo -e "- This utility is not compatible with Armada 37xx SoC family\n"
+fi
+
+# Sanity checks
+if [ -c "$port" ]
+then
+ echo -e "Using device connected on serial port \"$port\""
+else
+ echo "Wrong serial port name!"
+ exit 1
+fi
+
+if [ -f "$file" ]
+then
+ echo -e "Loading flash image file \"$file\""
+else
+ echo "File $file does not exist!"
+ exit 1
+fi
+
+# Verify required tools installation
+for tool in ${tools[@]}
+do
+ toolname=`which $tool`
+ if [ -z "$toolname" ]
+ then
+ echo -e "Missing installation of \"$tool\" --> Exiting"
+ exit 1
+ fi
+done
+
+
+echo -e "Recovery will run at $fast_baudrate baud"
+echo -e "========================================"
+
+if [ -f "$tmpfile" ]
+then
+ rm -f $tmpfile
+fi
+
+# Send the escape sequence to target board using default debug port speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+counter=0
+while [ $counter -lt $pattern_repeat ]; do
+ echo -n -e "$prefix\x11\x22\x33\x44\x55\x66\x77" >> $tmpfile
+ let counter=counter+1
+done
+
+echo -en "Press the \"Reset\" button on the target board and "
+echo -en "the \"Enter\" key on the host keyboard simultaneously"
+read
+dd if=$tmpfile of=$port &>/dev/null
+
+# Speed up the binary image transfer
+stty -F $port raw ignbrk time 5 $fast_baudrate
+sx -vv $file > $port < $port
+#sx-at91 $port $file
+
+# return the port to the default speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+
+# Optional - fire up Minicom
+minicom -D $port
+
projects / thirdparty / u-boot.git / commitdiff
