--- /dev/null
+From efbc74ace95338484f8d732037b99c7c77098fce Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Fri, 24 Feb 2012 12:12:38 +0100
+Subject: ARM: 7345/1: errata: update workaround for A9 erratum #743622
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit efbc74ace95338484f8d732037b99c7c77098fce upstream.
+
+Erratum #743622 affects all r2 variants of the Cortex-A9 processor, so
+ensure that the workaround is applied regardless of the revision.
+
+Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/Kconfig | 2 +-
+ arch/arm/mm/proc-v7.S | 4 +---
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1179,7 +1179,7 @@ config ARM_ERRATA_743622
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 743622 Cortex-A9
+- (r2p0..r2p2) erratum. Under very rare conditions, a faulty
++ (r2p*) erratum. Under very rare conditions, a faulty
+ optimisation in the Cortex-A9 Store Buffer may lead to data
+ corruption. This workaround sets a specific bit in the diagnostic
+ register of the Cortex-A9 which disables the Store Buffer
+--- a/arch/arm/mm/proc-v7.S
++++ b/arch/arm/mm/proc-v7.S
+@@ -344,9 +344,7 @@ __v7_setup:
+ mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
+ #endif
+ #ifdef CONFIG_ARM_ERRATA_743622
+- teq r6, #0x20 @ present in r2p0
+- teqne r6, #0x21 @ present in r2p1
+- teqne r6, #0x22 @ present in r2p2
++ teq r5, #0x00200000 @ only present in r2p*
+ mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
+ orreq r10, r10, #1 << 6 @ set bit #6
+ mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register