--- /dev/null
+From b07a657e3a05b81c8a30d60e3f3746ca5a48ee62 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali.rohar@gmail.com>
+Date: Mon, 11 Aug 2014 19:01:58 +0200
+Subject: drm/radeon: Add ability to get and change dpm state when radeon PX card is turned off
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali.rohar@gmail.com>
+
+commit b07a657e3a05b81c8a30d60e3f3746ca5a48ee62 upstream.
+
+This fixing commit 4f2f203976964e267dc477de6648bdb3acd2b74b
+
+bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=76321
+
+Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_pm.c | 16 ++++++----------
+ 1 file changed, 6 insertions(+), 10 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -460,10 +460,6 @@ static ssize_t radeon_get_dpm_state(stru
+ struct radeon_device *rdev = ddev->dev_private;
+ enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
+
+- if ((rdev->flags & RADEON_IS_PX) &&
+- (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+- return snprintf(buf, PAGE_SIZE, "off\n");
+-
+ return snprintf(buf, PAGE_SIZE, "%s\n",
+ (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
+ (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
+@@ -477,11 +473,6 @@ static ssize_t radeon_set_dpm_state(stru
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct radeon_device *rdev = ddev->dev_private;
+
+- /* Can't set dpm state when the card is off */
+- if ((rdev->flags & RADEON_IS_PX) &&
+- (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+- return -EINVAL;
+-
+ mutex_lock(&rdev->pm.mutex);
+ if (strncmp("battery", buf, strlen("battery")) == 0)
+ rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
+@@ -495,7 +486,12 @@ static ssize_t radeon_set_dpm_state(stru
+ goto fail;
+ }
+ mutex_unlock(&rdev->pm.mutex);
+- radeon_pm_compute_clocks(rdev);
++
++ /* Can't set dpm state when the card is off */
++ if (!(rdev->flags & RADEON_IS_PX) ||
++ (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
++ radeon_pm_compute_clocks(rdev);
++
+ fail:
+ return count;
+ }
--- /dev/null
+From 1952f24d0fa6292d65f886887af87ba8ac79b3ba Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 8 Sep 2014 13:55:51 -0400
+Subject: drm/radeon: add connector quirk for fujitsu board
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 1952f24d0fa6292d65f886887af87ba8ac79b3ba upstream.
+
+Vbios connector table lists non-existent VGA port.
+
+Bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=83184
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -447,6 +447,13 @@ static bool radeon_atom_apply_quirks(str
+ }
+ }
+
++ /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
++ if ((dev->pdev->device == 0x9805) &&
++ (dev->pdev->subsystem_vendor == 0x1734) &&
++ (dev->pdev->subsystem_device == 0x11bd)) {
++ if (*connector_type == DRM_MODE_CONNECTOR_VGA)
++ return false;
++ }
+
+ return true;
+ }
--- /dev/null
+From 6bce8d9772c1c606921a9c99e566eb14202f6669 Mon Sep 17 00:00:00 2001
+From: Oleg Chernovskiy <algonkvel@gmail.com>
+Date: Mon, 11 Aug 2014 21:53:46 +0400
+Subject: drm/radeon: Add missing lines to ci_set_thermal_temperature_range
+
+From: Oleg Chernovskiy <algonkvel@gmail.com>
+
+commit 6bce8d9772c1c606921a9c99e566eb14202f6669 upstream.
+
+Properly set the thermal min and max temp on CI.
+Otherwise, we end up setting the thermal ranges
+to 0 on resume and end up in the lowest power state.
+
+Signed-off-by: Oleg Chernovskiy <algonkvel@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ci_dpm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/ci_dpm.c
++++ b/drivers/gpu/drm/radeon/ci_dpm.c
+@@ -869,6 +869,9 @@ static int ci_set_thermal_temperature_ra
+ WREG32_SMC(CG_THERMAL_CTRL, tmp);
+ #endif
+
++ rdev->pm.dpm.thermal.min_temp = low_temp;
++ rdev->pm.dpm.thermal.max_temp = high_temp;
++
+ return 0;
+ }
+
--- /dev/null
+From 370ce45b5986118fa496dddbcd7039e1aa1a418f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Sep 2014 10:20:13 -0400
+Subject: drm/radeon/cik: use a separate counter for CP init timeout
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 370ce45b5986118fa496dddbcd7039e1aa1a418f upstream.
+
+Otherwise we may fail to init the second compute ring.
+
+Noticed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -4489,7 +4489,7 @@ struct bonaire_mqd
+ */
+ static int cik_cp_compute_resume(struct radeon_device *rdev)
+ {
+- int r, i, idx;
++ int r, i, j, idx;
+ u32 tmp;
+ bool use_doorbell = true;
+ u64 hqd_gpu_addr;
+@@ -4608,7 +4608,7 @@ static int cik_cp_compute_resume(struct
+ mqd->queue_state.cp_hqd_pq_wptr= 0;
+ if (RREG32(CP_HQD_ACTIVE) & 1) {
+ WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
+- for (i = 0; i < rdev->usec_timeout; i++) {
++ for (j = 0; j < rdev->usec_timeout; j++) {
+ if (!(RREG32(CP_HQD_ACTIVE) & 1))
+ break;
+ udelay(1);
--- /dev/null
+From 31a25e2caf9367365fcb0e57fd8fa5a42e9b73e4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 17 Sep 2014 17:41:04 -0400
+Subject: drm/radeon: don't reset dma on NI/SI init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 31a25e2caf9367365fcb0e57fd8fa5a42e9b73e4 upstream.
+
+Otherwise we may lose the DMA golden settings which can
+lead to hangs, etc.
+
+bug:
+https://www.libreoffice.org/bugzilla/show_bug.cgi?id=83500
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni_dma.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/ni_dma.c
++++ b/drivers/gpu/drm/radeon/ni_dma.c
+@@ -191,12 +191,6 @@ int cayman_dma_resume(struct radeon_devi
+ u32 reg_offset, wb_offset;
+ int i, r;
+
+- /* Reset dma */
+- WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
+- RREG32(SRBM_SOFT_RESET);
+- udelay(50);
+- WREG32(SRBM_SOFT_RESET, 0);
+-
+ for (i = 0; i < 2; i++) {
+ if (i == 0) {
+ ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
--- /dev/null
+From c1789a2e66a4209fe5035eca11fdd729b2ffdd82 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Sep 2014 10:23:04 -0400
+Subject: drm/radeon: don't reset dma on r6xx-evergreen init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit c1789a2e66a4209fe5035eca11fdd729b2ffdd82 upstream.
+
+Otherwise we may lose the DMA golden settings which can
+lead to hangs, etc.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r600_dma.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r600_dma.c
++++ b/drivers/gpu/drm/radeon/r600_dma.c
+@@ -124,15 +124,6 @@ int r600_dma_resume(struct radeon_device
+ u32 rb_bufsz;
+ int r;
+
+- /* Reset dma */
+- if (rdev->family >= CHIP_RV770)
+- WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
+- else
+- WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
+- RREG32(SRBM_SOFT_RESET);
+- udelay(50);
+- WREG32(SRBM_SOFT_RESET, 0);
+-
+ WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
+ WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
+
--- /dev/null
+From 799028d5d85384cce140323be633c8d5f079193f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Sep 2014 10:18:43 -0400
+Subject: drm/radeon: don't reset sdma on CIK init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 799028d5d85384cce140323be633c8d5f079193f upstream.
+
+Otherwise we may lose the DMA golden settings which can
+lead to hangs, etc.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik_sdma.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik_sdma.c
++++ b/drivers/gpu/drm/radeon/cik_sdma.c
+@@ -459,13 +459,6 @@ int cik_sdma_resume(struct radeon_device
+ {
+ int r;
+
+- /* Reset dma */
+- WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
+- RREG32(SRBM_SOFT_RESET);
+- udelay(50);
+- WREG32(SRBM_SOFT_RESET, 0);
+- RREG32(SRBM_SOFT_RESET);
+-
+ r = cik_sdma_load_microcode(rdev);
+ if (r)
+ return r;
--- /dev/null
+From 39da038479a81a35a7f8af3ab2c90effd5c8eff1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Sep 2014 11:16:31 -0400
+Subject: drm/radeon/dpm: fix resume on mullins
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 39da038479a81a35a7f8af3ab2c90effd5c8eff1 upstream.
+
+Need to properly disable nb dpm on dpm disable.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/kv_dpm.c | 28 +++++++++++++++++++++-------
+ 1 file changed, 21 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/kv_dpm.c
++++ b/drivers/gpu/drm/radeon/kv_dpm.c
+@@ -33,6 +33,8 @@
+ #define KV_MINIMUM_ENGINE_CLOCK 800
+ #define SMC_RAM_END 0x40000
+
++static int kv_enable_nb_dpm(struct radeon_device *rdev,
++ bool enable);
+ static void kv_init_graphics_levels(struct radeon_device *rdev);
+ static int kv_calculate_ds_divider(struct radeon_device *rdev);
+ static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
+@@ -1295,6 +1297,9 @@ void kv_dpm_disable(struct radeon_device
+ {
+ kv_smc_bapm_enable(rdev, false);
+
++ if (rdev->family == CHIP_MULLINS)
++ kv_enable_nb_dpm(rdev, false);
++
+ /* powerup blocks */
+ kv_dpm_powergate_acp(rdev, false);
+ kv_dpm_powergate_samu(rdev, false);
+@@ -1769,15 +1774,24 @@ static int kv_update_dfs_bypass_settings
+ return ret;
+ }
+
+-static int kv_enable_nb_dpm(struct radeon_device *rdev)
++static int kv_enable_nb_dpm(struct radeon_device *rdev,
++ bool enable)
+ {
+ struct kv_power_info *pi = kv_get_pi(rdev);
+ int ret = 0;
+
+- if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
+- ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
+- if (ret == 0)
+- pi->nb_dpm_enabled = true;
++ if (enable) {
++ if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
++ ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
++ if (ret == 0)
++ pi->nb_dpm_enabled = true;
++ }
++ } else {
++ if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
++ ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
++ if (ret == 0)
++ pi->nb_dpm_enabled = false;
++ }
+ }
+
+ return ret;
+@@ -1864,7 +1878,7 @@ int kv_dpm_set_power_state(struct radeon
+ }
+ kv_update_sclk_t(rdev);
+ if (rdev->family == CHIP_MULLINS)
+- kv_enable_nb_dpm(rdev);
++ kv_enable_nb_dpm(rdev, true);
+ }
+ } else {
+ if (pi->enable_dpm) {
+@@ -1889,7 +1903,7 @@ int kv_dpm_set_power_state(struct radeon
+ }
+ kv_update_acp_boot_level(rdev);
+ kv_update_sclk_t(rdev);
+- kv_enable_nb_dpm(rdev);
++ kv_enable_nb_dpm(rdev, true);
+ }
+ }
+
--- /dev/null
+From c83dec3bb6c38629398b65c231c80978b3e00e14 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 14 Aug 2014 01:22:31 -0400
+Subject: drm/radeon/dpm: select the appropriate vce power state for KV/KB/ML
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit c83dec3bb6c38629398b65c231c80978b3e00e14 upstream.
+
+Compare the clock in the limits table to the requested evclk rather
+than just taking the first value. Improves vce performance in certain
+cases.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/kv_dpm.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/kv_dpm.c
++++ b/drivers/gpu/drm/radeon/kv_dpm.c
+@@ -1438,14 +1438,14 @@ static int kv_update_uvd_dpm(struct rade
+ return kv_enable_uvd_dpm(rdev, !gate);
+ }
+
+-static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
++static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
+ {
+ u8 i;
+ struct radeon_vce_clock_voltage_dependency_table *table =
+ &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
+
+ for (i = 0; i < table->count; i++) {
+- if (table->entries[i].evclk >= 0) /* XXX */
++ if (table->entries[i].evclk >= evclk)
+ break;
+ }
+
+@@ -1468,7 +1468,7 @@ static int kv_update_vce_dpm(struct rade
+ if (pi->caps_stable_p_state)
+ pi->vce_boot_level = table->count - 1;
+ else
+- pi->vce_boot_level = kv_get_vce_boot_level(rdev);
++ pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
+
+ ret = kv_copy_bytes_to_smc(rdev,
+ pi->dpm_table_start +
--- /dev/null
+From ff4377924f7e587c61bcbc704eafecf6c7bd2e00 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 8 Sep 2014 02:33:32 -0400
+Subject: drm/radeon/dpm: set the thermal type properly for special configs
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit ff4377924f7e587c61bcbc704eafecf6c7bd2e00 upstream.
+
+On systems with special thermal configurations make sure we make
+note of the thermal setup. This is required for proper firmware
+configuration on these systems.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 26 +++++++++++++++++++-------
+ 1 file changed, 19 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -2281,19 +2281,31 @@ static void radeon_atombios_add_pplib_th
+ (controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+ rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
+- } else if ((controller->ucType ==
+- ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
+- (controller->ucType ==
+- ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
+- (controller->ucType ==
+- ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
+- DRM_INFO("Special thermal controller config\n");
++ } else if (controller->ucType ==
++ ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
++ DRM_INFO("External GPIO thermal controller %s fan control\n",
++ (controller->ucFanParameters &
++ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++ rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
++ } else if (controller->ucType ==
++ ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
++ DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
++ (controller->ucFanParameters &
++ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++ rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
++ } else if (controller->ucType ==
++ ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
++ DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
++ (controller->ucFanParameters &
++ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++ rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
+ } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
+ DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
+ pp_lib_thermal_controller_names[controller->ucType],
+ controller->ucI2cAddress >> 1,
+ (controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++ rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
+ i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
+ rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
+ if (rdev->pm.i2c_bus) {
--- /dev/null
+From 6101b3ae94b4f266456308824e9ca4eab1235d1a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 19 Aug 2014 11:54:15 -0400
+Subject: drm/radeon: fix active cu count for SI and CIK
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 6101b3ae94b4f266456308824e9ca4eab1235d1a upstream.
+
+This fixes the CU count reported to userspace for
+OpenCL.
+
+bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=82581
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik.c | 8 +++-----
+ drivers/gpu/drm/radeon/si.c | 8 +++-----
+ 2 files changed, 6 insertions(+), 10 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -3259,7 +3259,7 @@ static void cik_gpu_init(struct radeon_d
+ u32 mc_shared_chmap, mc_arb_ramcfg;
+ u32 hdp_host_path_cntl;
+ u32 tmp;
+- int i, j, k;
++ int i, j;
+
+ switch (rdev->family) {
+ case CHIP_BONAIRE:
+@@ -3451,10 +3451,8 @@ static void cik_gpu_init(struct radeon_d
+
+ for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
+ for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
+- for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {
+- rdev->config.cik.active_cus +=
+- hweight32(cik_get_cu_active_bitmap(rdev, i, j));
+- }
++ rdev->config.cik.active_cus +=
++ hweight32(cik_get_cu_active_bitmap(rdev, i, j));
+ }
+ }
+
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -2901,7 +2901,7 @@ static void si_gpu_init(struct radeon_de
+ u32 sx_debug_1;
+ u32 hdp_host_path_cntl;
+ u32 tmp;
+- int i, j, k;
++ int i, j;
+
+ switch (rdev->family) {
+ case CHIP_TAHITI:
+@@ -3101,10 +3101,8 @@ static void si_gpu_init(struct radeon_de
+
+ for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
+ for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
+- for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
+- rdev->config.si.active_cus +=
+- hweight32(si_get_cu_active_bitmap(rdev, i, j));
+- }
++ rdev->config.si.active_cus +=
++ hweight32(si_get_cu_active_bitmap(rdev, i, j));
+ }
+ }
+
--- /dev/null
+From 52da51f0f9ea9d213adfc99223630707b26d1d38 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 19 Aug 2014 11:56:38 -0400
+Subject: drm/radeon: fix active_cu mask on SI and CIK after re-init (v3)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 52da51f0f9ea9d213adfc99223630707b26d1d38 upstream.
+
+Need to initialize the mask to 0 on init, otherwise it
+keeps increasing.
+
+bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=82581
+
+v2: also fix cu count
+v3: split count fix into separate patch
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik.c | 1 +
+ drivers/gpu/drm/radeon/si.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -3449,6 +3449,7 @@ static void cik_gpu_init(struct radeon_d
+ rdev->config.cik.max_sh_per_se,
+ rdev->config.cik.max_backends_per_se);
+
++ rdev->config.cik.active_cus = 0;
+ for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
+ for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
+ rdev->config.cik.active_cus +=
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -3099,6 +3099,7 @@ static void si_gpu_init(struct radeon_de
+ rdev->config.si.max_sh_per_se,
+ rdev->config.si.max_cu_per_sh);
+
++ rdev->config.si.active_cus = 0;
+ for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
+ for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
+ rdev->config.si.active_cus +=
--- /dev/null
+From c940b4476f4fb649f6493b6a0ae837474ded8915 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 18 Aug 2014 11:57:28 -0400
+Subject: drm/radeon: fix pm handling in radeon_gpu_reset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit c940b4476f4fb649f6493b6a0ae837474ded8915 upstream.
+
+pm_suspend is handled in the radeon_suspend callbacks.
+pm_resume has special handling depending on whether
+dpm or legacy pm is enabled. Change radeon_gpu_reset
+to mirror the behavior in the suspend and resume
+pathes.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_device.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -1637,7 +1637,6 @@ int radeon_gpu_reset(struct radeon_devic
+ radeon_save_bios_scratch_regs(rdev);
+ /* block TTM */
+ resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
+- radeon_pm_suspend(rdev);
+ radeon_suspend(rdev);
+
+ for (i = 0; i < RADEON_NUM_RINGS; ++i) {
+@@ -1683,9 +1682,24 @@ retry:
+ }
+ }
+
+- radeon_pm_resume(rdev);
++ if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
++ /* do dpm late init */
++ r = radeon_pm_late_init(rdev);
++ if (r) {
++ rdev->pm.dpm_enabled = false;
++ DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
++ }
++ } else {
++ /* resume old pm late */
++ radeon_pm_resume(rdev);
++ }
++
+ drm_helper_resume_force_mode(rdev->ddev);
+
++ /* set the power state here in case we are a PX system or headless */
++ if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
++ radeon_pm_compute_clocks(rdev);
++
+ ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
+ if (r) {
+ /* bad news, how to tell it to userspace ? */
--- /dev/null
+From f229407da79315c18a2f25f485e1a1b9fdda1e92 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Sun, 7 Sep 2014 12:06:52 +0200
+Subject: drm/radeon: fix semaphore value init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+
+commit f229407da79315c18a2f25f485e1a1b9fdda1e92 upstream.
+
+Semaphore values have 64 bits, not 32. This fixes a very subtle bug
+that disables synchronization when the upper 32bits wasn't zero.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-By: Grigori Goronzy <greg@chown.ath.cx>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_semaphore.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_semaphore.c
++++ b/drivers/gpu/drm/radeon/radeon_semaphore.c
+@@ -34,7 +34,7 @@
+ int radeon_semaphore_create(struct radeon_device *rdev,
+ struct radeon_semaphore **semaphore)
+ {
+- uint32_t *cpu_addr;
++ uint64_t *cpu_addr;
+ int i, r;
+
+ *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);
--- /dev/null
+From 0a5f6e9d60e71e4b6dbeabd97bc887d6b2b0f0c8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 25 Aug 2014 14:52:15 -0400
+Subject: drm/radeon: handle broken disabled rb mask gracefully (6xx/7xx) (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 0a5f6e9d60e71e4b6dbeabd97bc887d6b2b0f0c8 upstream.
+
+This is a port of cedb655a3a7764c3fd946077944383c9e0e68dd4
+to older asics. Fixes a possible divide by 0 if the harvest
+register is invalid.
+
+v2: drop some additional harvest munging.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r600.c | 26 ++++++++------------------
+ drivers/gpu/drm/radeon/rv770.c | 23 ++++++++---------------
+ 2 files changed, 16 insertions(+), 33 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r600.c
++++ b/drivers/gpu/drm/radeon/r600.c
+@@ -1813,7 +1813,6 @@ static void r600_gpu_init(struct radeon_
+ {
+ u32 tiling_config;
+ u32 ramcfg;
+- u32 cc_rb_backend_disable;
+ u32 cc_gc_shader_pipe_config;
+ u32 tmp;
+ int i, j;
+@@ -1940,29 +1939,20 @@ static void r600_gpu_init(struct radeon_
+ }
+ tiling_config |= BANK_SWAPS(1);
+
+- cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
+- tmp = R6XX_MAX_BACKENDS -
+- r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
+- if (tmp < rdev->config.r600.max_backends) {
+- rdev->config.r600.max_backends = tmp;
+- }
+-
+ cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
+- tmp = R6XX_MAX_PIPES -
+- r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
+- if (tmp < rdev->config.r600.max_pipes) {
+- rdev->config.r600.max_pipes = tmp;
+- }
+- tmp = R6XX_MAX_SIMDS -
+- r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
+- if (tmp < rdev->config.r600.max_simds) {
+- rdev->config.r600.max_simds = tmp;
+- }
+ tmp = rdev->config.r600.max_simds -
+ r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
+ rdev->config.r600.active_simds = tmp;
+
+ disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
++ tmp = 0;
++ for (i = 0; i < rdev->config.r600.max_backends; i++)
++ tmp |= (1 << i);
++ /* if all the backends are disabled, fix it up here */
++ if ((disabled_rb_mask & tmp) == tmp) {
++ for (i = 0; i < rdev->config.r600.max_backends; i++)
++ disabled_rb_mask &= ~(1 << i);
++ }
+ tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
+ tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
+ R6XX_MAX_BACKENDS, disabled_rb_mask);
+--- a/drivers/gpu/drm/radeon/rv770.c
++++ b/drivers/gpu/drm/radeon/rv770.c
+@@ -1178,7 +1178,6 @@ static void rv770_gpu_init(struct radeon
+ u32 hdp_host_path_cntl;
+ u32 sq_dyn_gpr_size_simd_ab_0;
+ u32 gb_tiling_config = 0;
+- u32 cc_rb_backend_disable = 0;
+ u32 cc_gc_shader_pipe_config = 0;
+ u32 mc_arb_ramcfg;
+ u32 db_debug4, tmp;
+@@ -1312,21 +1311,7 @@ static void rv770_gpu_init(struct radeon
+ WREG32(SPI_CONFIG_CNTL, 0);
+ }
+
+- cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
+- tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
+- if (tmp < rdev->config.rv770.max_backends) {
+- rdev->config.rv770.max_backends = tmp;
+- }
+-
+ cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
+- tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
+- if (tmp < rdev->config.rv770.max_pipes) {
+- rdev->config.rv770.max_pipes = tmp;
+- }
+- tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
+- if (tmp < rdev->config.rv770.max_simds) {
+- rdev->config.rv770.max_simds = tmp;
+- }
+ tmp = rdev->config.rv770.max_simds -
+ r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
+ rdev->config.rv770.active_simds = tmp;
+@@ -1349,6 +1334,14 @@ static void rv770_gpu_init(struct radeon
+ rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
+
+ disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
++ tmp = 0;
++ for (i = 0; i < rdev->config.rv770.max_backends; i++)
++ tmp |= (1 << i);
++ /* if all the backends are disabled, fix it up here */
++ if ((disabled_rb_mask & tmp) == tmp) {
++ for (i = 0; i < rdev->config.rv770.max_backends; i++)
++ disabled_rb_mask &= ~(1 << i);
++ }
+ tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
+ tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
+ R7XX_MAX_BACKENDS, disabled_rb_mask);
--- /dev/null
+From 701e1e789142042144c8cc10b8f6d1554e960144 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 15 Aug 2014 11:52:53 +0200
+Subject: drm/radeon: properly document reloc priority mask
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+
+commit 701e1e789142042144c8cc10b8f6d1554e960144 upstream.
+
+Instead of hard coding the value properly document
+that this is an userspace interface.
+
+No intended functional change.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_cs.c | 3 ++-
+ include/uapi/drm/radeon_drm.h | 1 +
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_cs.c
++++ b/drivers/gpu/drm/radeon/radeon_cs.c
+@@ -132,7 +132,8 @@ static int radeon_cs_parser_relocs(struc
+ * the buffers used for read only, which doubles the range
+ * to 0 to 31. 32 is reserved for the kernel driver.
+ */
+- priority = (r->flags & 0xf) * 2 + !!r->write_domain;
++ priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
++ + !!r->write_domain;
+
+ /* the first reloc of an UVD job is the msg and that must be in
+ VRAM, also but everything into VRAM on AGP cards to avoid
+--- a/include/uapi/drm/radeon_drm.h
++++ b/include/uapi/drm/radeon_drm.h
+@@ -942,6 +942,7 @@ struct drm_radeon_cs_chunk {
+ };
+
+ /* drm_radeon_cs_reloc.flags */
++#define RADEON_RELOC_PRIO_MASK (0xf << 0)
+
+ struct drm_radeon_cs_reloc {
+ uint32_t handle;
imx-drm-ipuv3-plane-fix-ipu_plane_dpms.patch
imx-drm-imx-ldb-fix-null-pointer-in-imx_ldb_unbind.patch
drm-vmwgfx-fix-a-potential-infinite-spin-waiting-for-fifo-idle.patch
+drm-radeon-add-ability-to-get-and-change-dpm-state-when-radeon-px-card-is-turned-off.patch
+drm-radeon-add-missing-lines-to-ci_set_thermal_temperature_range.patch
+drm-radeon-dpm-select-the-appropriate-vce-power-state-for-kv-kb-ml.patch
+drm-radeon-properly-document-reloc-priority-mask.patch
+drm-radeon-fix-pm-handling-in-radeon_gpu_reset.patch
+drm-radeon-fix-active-cu-count-for-si-and-cik.patch
+drm-radeon-fix-active_cu-mask-on-si-and-cik-after-re-init-v3.patch
+drm-radeon-handle-broken-disabled-rb-mask-gracefully-6xx-7xx-v2.patch
+drm-radeon-fix-semaphore-value-init.patch
+drm-radeon-dpm-set-the-thermal-type-properly-for-special-configs.patch
+drm-radeon-add-connector-quirk-for-fujitsu-board.patch
+drm-radeon-don-t-reset-dma-on-ni-si-init.patch
+drm-radeon-don-t-reset-sdma-on-cik-init.patch
+drm-radeon-don-t-reset-dma-on-r6xx-evergreen-init.patch
+drm-radeon-dpm-fix-resume-on-mullins.patch
+drm-radeon-cik-use-a-separate-counter-for-cp-init-timeout.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
