RISC-V: Fix RVV related testsuite

Use wrapper of riscv_vector.h for RVV related testcases,
more detail see https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to
	include riscv_vector.h rather than angle brackets.
	* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-13.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-7.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
	* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
	* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e308f9042c9ac49db9f184040355c292094..cfc565b89222476fcc55522c5027cb089150d132 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa8297c30f6cd97e1e057d47ea0e2743a37702..419f19d01846a619842f29407c07f9f014018240 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb6b9359ffa5034f9454f8e3f805bed69f6..1bb159c7099f1df1f510ed4d18557547c53922c6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40b62d40bbfd08d710f2842fc3086d7f327..7886886e2f53a95ce3deedd866592ed254afe071 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov14:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3bedb7945645cbb926fd50a03e7859b981..9515e07eca19c82d35a335e8ce611c603357e271 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 void mov1 (int8_t *in, int8_t *out) 
 { 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd515747ec6c01e14ab262ee63a21de4c9e7f..301607a2906c65fcad065540a7c416e8bfcfa3de 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov2:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db2735f6654a0f4d249c4c60c156ae208d8..ea69ab2dbd5744b6ac7a53cb1bf44ae0bc5ef840 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b10b4557ee5d713a3fa3fd7a96cf5de3c8..50bbd10669241d138c8eb31b75e5223dee37de65 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232ba86793d46d44c270f90fc178c642e2281..680b4f428421c4bfcaa4b3795e069bab3d05d2f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73bb099a05ac62b5e4c274efc08509d1f9b9..6348b38d9d7c15688dffb453da0d59f089715951 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0adfbc9bdf26f8892d691dc296151a7ebc..c60920a88477dec6fb5b8c240c1ae5b30fa7b31c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* This testcase is testing whether RISC-V define REGMODE_NATURAL_SIZE.  */
 void foo (int8_t *in, int8_t *out)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05899d59993c1e7014fd1b203abff6a0979..f2cb244473f0109edaa7d87f2d9f329647a466cf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c0f4df4b08597d3367dd913087ec551d07..902d65eb503b75380d02c69400cb1ea993310bd0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* Test tieable of RVV types with same LMUL.  */
 /*

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
index fa643c58785716ce1cff9e8a1d5a25a83a23cb83..69c9c1fa5ca64e2434b4ba7ea22f05e273b6c496 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 unsigned long vread_csr_vstart(void) {
   return vread_csr(RVV_VSTART);

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9170e207a32484e28917c21c525bb9d71d..60d3b4997197d6178b221a056764588f99774fa0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
 #include <stddef.h>
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 size_t test_vsetvl_e8mf8_imm0()
 {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
index e23da4b12ea4d2a6b66e02be9a6dad37181e9f06..f9b4e8848df88551244189fbe1134243b501daa3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 void vwrite_csr_vstart(unsigned long value) {
   vwrite_csr(RVV_VSTART, value);