arm64: dts: ti: k3-j721e-sk*: Add bootph-* properties

Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.

Following adds bootph-* to:
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc1, usb0, usb1, ospi0 for enabling various bootmodes.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-11-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 6285e8d94ddeb75003468176bfbad7150c77facf..69b3d1ed8a21c26916721be6d10af1ba63ded156 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -346,6 +346,7 @@
                        J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
                        J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
                >;
+               bootph-all;
        };
 
        main_uart0_pins_default: main-uart0-default-pins {
@@ -355,6 +356,7 @@
                        J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
                        J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
                >;
+               bootph-all;
        };
 
        main_uart1_pins_default: main-uart1-default-pins {
@@ -390,12 +392,14 @@
                        J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
                        J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
                >;
+               bootph-all;
        };
 
        main_usbss1_pins_default: main-usbss1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
                >;
+               bootph-all;
        };
 
        main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
@@ -594,6 +598,7 @@
                        J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
                        J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
                >;
+               bootph-all;
        };
 
        vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
@@ -622,6 +627,7 @@
                        J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
                        J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
                >;
+               bootph-all;
        };
 
        wkup_i2c0_pins_default: wkup-i2c0-default-pins {
@@ -629,6 +635,7 @@
                        J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
                        J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
                >;
+               bootph-all;
        };
 
        mcu_mcan0_pins_default: mcu-mcan0-default-pins {
@@ -657,6 +664,7 @@
        status = "reserved";
        pinctrl-names = "default";
        pinctrl-0 = <&wkup_uart0_pins_default>;
+       bootph-all;
 };
 
 &wkup_i2c0 {
@@ -821,6 +829,7 @@
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_uart0_pins_default>;
+       bootph-all;
 };
 
 &main_uart0 {
@@ -829,6 +838,7 @@
        pinctrl-0 = <&main_uart0_pins_default>;
        /* Shared with ATF on this platform */
        power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+       bootph-all;
 };
 
 &main_uart1 {
@@ -844,6 +854,7 @@
        vqmmc-supply = <&vdd_sd_dv_alt>;
        pinctrl-names = "default";
        pinctrl-0 = <&main_mmc1_pins_default>;
+       bootph-all;
        ti,driver-strength-ohm = <50>;
        disable-wp;
 };
@@ -908,6 +919,7 @@
                        partition@3fc0000 {
                                label = "ospi.phypattern";
                                reg = <0x3fc0000 0x40000>;
+                               bootph-all;
                        };
                };
        };
@@ -1003,6 +1015,7 @@
 
 &usb_serdes_mux {
        idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+       bootph-all;
 };
 
 &serdes_ln_ctrl {
@@ -1012,6 +1025,7 @@
                      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
                      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
                      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+       bootph-all;
 };
 
 &serdes_wiz3 {
@@ -1050,6 +1064,7 @@
 &usbss0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss0_pins_default>;
+       bootph-all;
        ti,vbus-divider;
 };
 
@@ -1058,6 +1073,7 @@
        maximum-speed = "super-speed";
        phys = <&serdes3_usb_link>;
        phy-names = "cdns3,usb3-phy";
+       bootph-all;
 };
 
 &serdes2 {
@@ -1073,6 +1089,7 @@
 &usbss1 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss1_pins_default>;
+       bootph-all;
        ti,vbus-divider;
 };
 
@@ -1081,6 +1098,7 @@
        maximum-speed = "super-speed";
        phys = <&serdes2_usb_link>;
        phy-names = "cdns3,usb3-phy";
+       bootph-all;
 };
 
 &mcu_cpsw {