]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/riscv: fix clzw implementation to operate on arg1
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Sat, 11 Sep 2021 14:00:02 +0000 (16:00 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 6 Oct 2021 22:32:39 +0000 (08:32 +1000)
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvb.c.inc

index c0a6e25826eb2c35ce64a67ec4567ba6cc903e46..6c85c89f6d433d8413f71829bcaacb48c2221008 100644 (file)
@@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-    tcg_gen_clzi_tl(ret, ret, 64);
+    tcg_gen_clzi_tl(ret, arg1, 64);
     tcg_gen_subi_tl(ret, ret, 32);
 }