amd-xgbe: add support for new XPCS routines

Add the necessary support to enable Renoir ethernet device. Since the
BAR1 address cannot be used to access the XPCS registers on Renoir, use
the smn functions.

Some of the ethernet add-in-cards have dual PHY but share a single MDIO
line (between the ports). In such cases, link inconsistencies are
noticed during the heavy traffic and during reboot stress tests. Using
smn calls helps avoid such race conditions.

Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250509155325.720499-4-Raju.Rangoju@amd.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index cdab1c24dd699283ff3e9625267a4b99842ea12f..466b5f6e55789d6c6aacb310ada98dea0fc0b8e8 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -11,9 +11,11 @@
 #include <linux/bitrev.h>
 #include <linux/crc32.h>
 #include <linux/crc32poly.h>
+#include <linux/pci.h>
 
 #include "xgbe.h"
 #include "xgbe-common.h"
+#include "xgbe-smn.h"
 
 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
 {
@@ -1080,6 +1082,84 @@ static void xgbe_get_pcs_index_and_offset(struct xgbe_prv_data *pdata,
        *offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
 }
 
+static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
+                                int mmd_reg)
+{
+       unsigned int mmd_address, index, offset;
+       u32 smn_address;
+       int mmd_data;
+       int ret;
+
+       mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
+
+       xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
+
+       smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg;
+       ret = amd_smn_write(0, smn_address, index);
+       if (ret)
+               return ret;
+
+       ret = amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
+       if (ret)
+               return ret;
+
+       mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
+                                 FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
+
+       return mmd_data;
+}
+
+static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
+                                  int mmd_reg, int mmd_data)
+{
+       unsigned int pci_mmd_data, hi_mask, lo_mask;
+       unsigned int mmd_address, index, offset;
+       struct pci_dev *dev;
+       u32 smn_address;
+       int ret;
+
+       dev = pdata->pcidev;
+       mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
+
+       xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
+
+       smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg;
+       ret = amd_smn_write(0, smn_address, index);
+       if (ret) {
+               pci_err(dev, "Failed to write data 0x%x\n", index);
+               return;
+       }
+
+       ret = amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data);
+       if (ret) {
+               pci_err(dev, "Failed to read data\n");
+               return;
+       }
+
+       if (offset % 4) {
+               hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data);
+               lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, pci_mmd_data);
+       } else {
+               hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK,
+                                    FIELD_GET(XGBE_GEN_HI_MASK, pci_mmd_data));
+               lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
+       }
+
+       pci_mmd_data = hi_mask | lo_mask;
+
+       ret = amd_smn_write(0, smn_address, index);
+       if (ret) {
+               pci_err(dev, "Failed to write data 0x%x\n", index);
+               return;
+       }
+
+       ret = amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data);
+       if (ret) {
+               pci_err(dev, "Failed to write data 0x%x\n", pci_mmd_data);
+               return;
+       }
+}
+
 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
                                 int mmd_reg)
 {
@@ -1174,6 +1254,9 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
        case XGBE_XPCS_ACCESS_V2:
        default:
                return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
+
+       case XGBE_XPCS_ACCESS_V3:
+               return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg);
        }
 }
 
@@ -1184,6 +1267,9 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
        case XGBE_XPCS_ACCESS_V1:
                return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data);
 
+       case XGBE_XPCS_ACCESS_V3:
+               return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data);
+
        case XGBE_XPCS_ACCESS_V2:
        default:
                return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-smn.h b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
new file mode 100644 (file)
index 0000000..3fd03d3
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
+ * Copyright (c) 2014, Synopsys, Inc.
+ * All rights reserved
+ *
+ * Author: Raju Rangoju <Raju.Rangoju@amd.com>
+ */
+
+#ifndef __SMN_H__
+#define __SMN_H__
+
+#ifdef CONFIG_AMD_NB
+
+#include <asm/amd_nb.h>
+
+#else
+
+static inline int amd_smn_write(u16 node, u32 address, u32 value)
+{
+       return -ENODEV;
+}
+
+static inline int amd_smn_read(u16 node, u32 address, u32 *value)
+{
+       return -ENODEV;
+}
+
+#endif
+#endif

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 37e5f8fad6b245f96df2f449cf5fcaef6bd6df0d..44ba6b02cdeb294d062db73e1a10810a0397bc39 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -242,6 +242,10 @@
 #define XGBE_RV_PCI_DEVICE_ID  0x15d0
 #define XGBE_YC_PCI_DEVICE_ID  0x14b5
 
+ /* Generic low and high masks */
+#define XGBE_GEN_HI_MASK       GENMASK(31, 16)
+#define XGBE_GEN_LO_MASK       GENMASK(15, 0)
+
 struct xgbe_prv_data;
 
 struct xgbe_packet_data {
@@ -460,6 +464,7 @@ enum xgbe_speed {
 enum xgbe_xpcs_access {
        XGBE_XPCS_ACCESS_V1 = 0,
        XGBE_XPCS_ACCESS_V2,
+       XGBE_XPCS_ACCESS_V3,
 };
 
 enum xgbe_an_mode {
@@ -955,6 +960,7 @@ struct xgbe_prv_data {
        struct device *dev;
        struct platform_device *phy_platdev;
        struct device *phy_dev;
+       unsigned int smn_base;
 
        /* Version related data */
        struct xgbe_version_data *vdata;